staging: dt3155: revert u_long to u64 usage

Commit 9c1390a923ddb6fba1cf9d7440743369140c6d8a replaced
all u_int's with u32 and u_long's with u64. Unfortunately, a u_long
is still only 32-bits so they should have been replaced with u32 also.

This can be verified by the register definitions in dt3155_io.h.  It
specifically states that the memory mapped registers are 32-bit.

Fix this by changing all the u64 to u32.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Greg Kroah-Hartman <greg@kroah.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 8 insertions, 8 deletions

diff --git a/drivers/staging/dt3155/dt3155_io.c b/drivers/staging/dt3155/dt3155_io.c
index 1c15604..6b9c685 100644
--- a/drivers/staging/dt3155/dt3155_io.c
+++ b/drivers/staging/dt3155/dt3155_io.c
@@ -27,12 +27,12 @@
 
 
 /****** local copies of board's 32 bit registers ******/
-u64 even_dma_start_r;	/*  bit 0 should always be 0 */
-u64 odd_dma_start_r;	/*               .. */
-u64 even_dma_stride_r;	/*  bits 0&1 should always be 0 */
-u64 odd_dma_stride_r;	/*               .. */
-u64 even_pixel_fmt_r;
-u64 odd_pixel_fmt_r;
+u32 even_dma_start_r;	/*  bit 0 should always be 0 */
+u32 odd_dma_start_r;	/*               .. */
+u32 even_dma_stride_r;	/*  bits 0&1 should always be 0 */
+u32 odd_dma_stride_r;	/*               .. */
+u32 even_pixel_fmt_r;
+u32 odd_pixel_fmt_r;
 
 FIFO_TRIGGER_R		fifo_trigger_r;
 XFER_MODE_R		xfer_mode_r;
@@ -40,8 +40,8 @@ CSR1_R			csr1_r;
 RETRY_WAIT_CNT_R	retry_wait_cnt_r;
 INT_CSR_R		int_csr_r;
 
-u64 even_fld_mask_r;
-u64 odd_fld_mask_r;
+u32 even_fld_mask_r;
+u32 odd_fld_mask_r;
 
 MASK_LENGTH_R		mask_length_r;
 FIFO_FLAG_CNT_R		fifo_flag_cnt_r;