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authorRafał Miłecki <zajec5@gmail.com>2011-05-11 02:10:58 +0200
committerJohn W. Linville <linville@tuxdriver.com>2011-05-11 14:50:41 -0400
commit8576f815d5c8beb8b10f96abe31831b90af3d352 (patch)
tree5c600a151f8a508434e20d8ade1579c0c4cec696 /drivers/ssb/main.c
parent1073e4ee595265086a592a056d903bf4fcc8885a (diff)
downloadop-kernel-dev-8576f815d5c8beb8b10f96abe31831b90af3d352.zip
op-kernel-dev-8576f815d5c8beb8b10f96abe31831b90af3d352.tar.gz
ssb: move ssb_commit_settings and export it
Commiting settings is possible on devices without PCI core (but with CC core). Export it for usage in drivers supporting other cores. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/ssb/main.c')
-rw-r--r--drivers/ssb/main.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
index ad3da93..ee2937c 100644
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -1329,6 +1329,31 @@ error:
}
EXPORT_SYMBOL(ssb_bus_powerup);
+static void ssb_broadcast_value(struct ssb_device *dev,
+ u32 address, u32 data)
+{
+ /* This is used for both, PCI and ChipCommon core, so be careful. */
+ BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+ BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+
+ ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
+ ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
+ ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
+ ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
+}
+
+void ssb_commit_settings(struct ssb_bus *bus)
+{
+ struct ssb_device *dev;
+
+ dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+ if (WARN_ON(!dev))
+ return;
+ /* This forces an update of the cached registers. */
+ ssb_broadcast_value(dev, 0xFD8, 0);
+}
+EXPORT_SYMBOL(ssb_commit_settings);
+
u32 ssb_admatch_base(u32 adm)
{
u32 base = 0;
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