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authorMichael Buesch <mb@bu3sch.de>2008-02-19 14:53:35 +0100
committerJohn W. Linville <linville@tuxdriver.com>2008-02-20 20:11:49 -0500
commitc2bcbe65fc88d61f9a806367ff6eab76c9eabb3a (patch)
treec882d3016ed4a273b8e7e8fb9b86c1bcb6d6836a /drivers/ssb/driver_chipcommon.c
parent42bfad4f71637c4eb4791aa8062063c4a8526522 (diff)
downloadop-kernel-dev-c2bcbe65fc88d61f9a806367ff6eab76c9eabb3a.zip
op-kernel-dev-c2bcbe65fc88d61f9a806367ff6eab76c9eabb3a.tar.gz
ssb: Fix the GPIO API
This fixes the GPIO API to be usable. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/ssb/driver_chipcommon.c')
-rw-r--r--drivers/ssb/driver_chipcommon.c35
1 files changed, 29 insertions, 6 deletions
diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c
index 7cc03f2..7ea0c0f 100644
--- a/drivers/ssb/driver_chipcommon.c
+++ b/drivers/ssb/driver_chipcommon.c
@@ -39,12 +39,14 @@ static inline void chipco_write32(struct ssb_chipcommon *cc,
ssb_write32(cc->dev, offset, value);
}
-static inline void chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
- u32 mask, u32 value)
+static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
+ u32 mask, u32 value)
{
value &= mask;
value |= chipco_read32(cc, offset) & ~mask;
chipco_write32(cc, offset, value);
+
+ return value;
}
void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
@@ -355,16 +357,37 @@ u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
{
return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
}
+EXPORT_SYMBOL(ssb_chipco_gpio_in);
+
+u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
+{
+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
+}
+EXPORT_SYMBOL(ssb_chipco_gpio_out);
+
+u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
+{
+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
+}
+EXPORT_SYMBOL(ssb_chipco_gpio_outen);
+
+u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
+{
+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
+}
+EXPORT_SYMBOL(ssb_chipco_gpio_control);
-void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
+u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
{
- chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
}
+EXPORT_SYMBOL(ssb_chipco_gpio_intmask);
-void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
+u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
{
- chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
}
+EXPORT_SYMBOL(ssb_chipco_gpio_polarity);
#ifdef CONFIG_SSB_SERIAL
int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
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