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| author | Leilk Liu <leilk.liu@mediatek.com> | 2015-08-31 21:18:57 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-08-31 15:26:50 +0100 |
| commit | adcbcfea15d62fab5ba40ac28f9d2a590cc5e5e8 (patch) | |
| tree | 5c9d4db20afeb1b95bc03efb49ba3237c4023bcd /drivers/spi/spi-tegra20-slink.c | |
| parent | ca9f26a27949ba3b295e4f0841c0bec9ef440141 (diff) | |
| download | op-kernel-dev-adcbcfea15d62fab5ba40ac28f9d2a590cc5e5e8.zip op-kernel-dev-adcbcfea15d62fab5ba40ac28f9d2a590cc5e5e8.tar.gz | |
spi: mediatek: fix spi clock usage error
spi clock manages flow:
CLK_TOP_SYSPLL3_D2 ---> CLK_TOP_SPI_SEL ---> CLK_PERI_SPI0
(source clock) (clock mux) (clock gate)
spi driver should choose source clock by clock mux, then enable
clock gate.
Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-tegra20-slink.c')
0 files changed, 0 insertions, 0 deletions
