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authorPaul Mundt <lethal@linux-sh.org>2008-11-13 17:46:06 +0900
committerPaul Mundt <lethal@linux-sh.org>2008-11-13 17:46:06 +0900
commit272966c070237c8cb540fe67e06df51bc6ea9cc2 (patch)
tree2937aa90cd6c972b13f0173f60e76c186111ffaf /drivers/serial
parent5d52013cbb3d39bde9f5a6023193058eeb112e98 (diff)
downloadop-kernel-dev-272966c070237c8cb540fe67e06df51bc6ea9cc2.zip
op-kernel-dev-272966c070237c8cb540fe67e06df51bc6ea9cc2.tar.gz
serial: sh-sci: Reorder the SCxTDR write after the TDxE clear.
Under qemu there is a race between the TDxE read-and-clear and the SCxTDR write. While on hardware it can be gauranteed that the read-and-clear will happen prior to the character being written out, no such assumption can be made under emulation. As this path happens with IRQs off and the hardware itself doesn't care about the ordering, move the SCxTDR write until after the read-and-clear. Signed-off-by: Vladimir Prus <vladimir@codesourcery.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/sh-sci.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 518c032..165fc01 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -144,9 +144,9 @@ static void put_char(struct uart_port *port, char c)
status = sci_in(port, SCxSR);
} while (!(status & SCxSR_TDxE(port)));
- sci_out(port, SCxTDR, c);
sci_in(port, SCxSR); /* Dummy read */
sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
+ sci_out(port, SCxTDR, c);
spin_unlock_irqrestore(&port->lock, flags);
}
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