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| author | Richard Röjfors <richard.rojfors@pelagicore.com> | 2010-04-27 14:16:34 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-05-21 09:34:29 -0700 |
| commit | 24cd73a3942f3df214d7953f0cfd65d5085fa583 (patch) | |
| tree | ead53b3f9d40915b629fdcef2e2af89c21c66b0b /drivers/serial | |
| parent | 44051996230510ccb125cfa552d464950d1767b9 (diff) | |
| download | op-kernel-dev-24cd73a3942f3df214d7953f0cfd65d5085fa583.zip op-kernel-dev-24cd73a3942f3df214d7953f0cfd65d5085fa583.tar.gz | |
serial: timbuart: make sure last byte is sent when port is closed
Fix a problem in early versions of the FPGA IP.
In certain situations the IP reports that the FIFO is empty, but a byte is
still clocked out. If a flush is done at that point the currently clocked
byte is canceled.
This causes incompatibilities with the upper layers when a port is closed,
it waits until the FIFO is empty and then closes the port. During close
the FIFO is flushed -> the last byte is not sent properly.
Now the FIFO is only flushed if it is reported to be non-empty. Which
makes the currently clocked out byte to finish.
[akpm@linux-foundation.org: fix build]
Signed-off-by: Richard Röjfors <richard.rojfors@pelagicore.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/serial')
| -rw-r--r-- | drivers/serial/timbuart.c | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/drivers/serial/timbuart.c b/drivers/serial/timbuart.c index 62f389f..67ca642 100644 --- a/drivers/serial/timbuart.c +++ b/drivers/serial/timbuart.c @@ -68,12 +68,22 @@ static void timbuart_start_tx(struct uart_port *port) tasklet_schedule(&uart->tasklet); } +static unsigned int timbuart_tx_empty(struct uart_port *port) +{ + u32 isr = ioread32(port->membase + TIMBUART_ISR); + + return (isr & TXBE) ? TIOCSER_TEMT : 0; +} + static void timbuart_flush_buffer(struct uart_port *port) { - u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | TIMBUART_CTRL_FLSHTX; + if (!timbuart_tx_empty(port)) { + u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | + TIMBUART_CTRL_FLSHTX; - iowrite8(ctl, port->membase + TIMBUART_CTRL); - iowrite32(TXBF, port->membase + TIMBUART_ISR); + iowrite8(ctl, port->membase + TIMBUART_CTRL); + iowrite32(TXBF, port->membase + TIMBUART_ISR); + } } static void timbuart_rx_chars(struct uart_port *port) @@ -195,13 +205,6 @@ void timbuart_tasklet(unsigned long arg) dev_dbg(uart->port.dev, "%s leaving\n", __func__); } -static unsigned int timbuart_tx_empty(struct uart_port *port) -{ - u32 isr = ioread32(port->membase + TIMBUART_ISR); - - return (isr & TXBE) ? TIOCSER_TEMT : 0; -} - static unsigned int timbuart_get_mctrl(struct uart_port *port) { u8 cts = ioread8(port->membase + TIMBUART_CTRL); |
