diff options
| author | Dave Liu <daveliu@freescale.com> | 2009-06-08 22:24:36 +0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-06-15 21:45:31 -0500 |
| commit | b45cc9eff72e0871ffb83ae32c3dbca382909706 (patch) | |
| tree | 37e070b812470b5dcff069eba73c0cb39afb15f7 /drivers/serial/ucc_uart.c | |
| parent | f1f8b4948d19ae84fe37e36601ae064102dfa5ab (diff) | |
| download | op-kernel-dev-b45cc9eff72e0871ffb83ae32c3dbca382909706.zip op-kernel-dev-b45cc9eff72e0871ffb83ae32c3dbca382909706.tar.gz | |
serial: Make ucc_uart work in HW UART mode
In HW UART mode the TxBD[READY] is not cleared by H/W (RISC engine) when
the user send characters to Tx buffer of QE UART. So, these characters
stay on the QE forever, never go to UART line.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers/serial/ucc_uart.c')
| -rw-r--r-- | drivers/serial/ucc_uart.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/drivers/serial/ucc_uart.c b/drivers/serial/ucc_uart.c index 7de66c0..e945e78 100644 --- a/drivers/serial/ucc_uart.c +++ b/drivers/serial/ucc_uart.c @@ -681,22 +681,27 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port) out_be16(&uccup->rccm, 0xc0ff); /* Configure the GUMR registers for UART */ - if (soft_uart) + if (soft_uart) { /* Soft-UART requires a 1X multiplier for TX */ clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK, UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16); - else + + clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW, + UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX); + } else { clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK, UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16); - clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW, - UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX); + clrsetbits_be32(&uccp->gumr_h, + UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX, + UCC_SLOW_GUMR_H_RFW); + } #ifdef LOOPBACK clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, @@ -706,7 +711,7 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port) UCC_SLOW_GUMR_H_CDS); #endif - /* Enable rx interrupts and clear all pending events. */ + /* Disable rx interrupts and clear all pending events. */ out_be16(&uccp->uccm, 0); out_be16(&uccp->ucce, 0xffff); out_be16(&uccp->udsr, 0x7e7e); @@ -765,6 +770,10 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port) cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, QE_CR_PROTOCOL_UNSPECIFIED, 0); + } else { + cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); + qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, + QE_CR_PROTOCOL_UART, 0); } } |
