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| author | Haavard Skinnemoen <hskinnemoen@atmel.com> | 2007-02-12 00:52:15 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-12 09:48:29 -0800 |
| commit | 544fc7283cd6902831d660bd8e1181602bd2b4d2 (patch) | |
| tree | 4047a09e91eb833807caa2e9de07e05f38df3609 /drivers/serial/atmel_serial.c | |
| parent | 3991d3bd1506391d8feec209b1d22ccb1c03a0bf (diff) | |
| download | op-kernel-dev-544fc7283cd6902831d660bd8e1181602bd2b4d2.zip op-kernel-dev-544fc7283cd6902831d660bd8e1181602bd2b4d2.tar.gz | |
[PATCH] atmel_serial: Use __raw I/O register access
Access to chip-internal registers should always be native-endian. This is
especially important for AVR32 since it's a big-endian architecture and the
non-raw readl() and writel() macros are defined to do little-endian
accesses.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Acked-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/serial/atmel_serial.c')
| -rw-r--r-- | drivers/serial/atmel_serial.c | 54 |
1 files changed, 27 insertions, 27 deletions
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c index 881f886..df45a7a 100644 --- a/drivers/serial/atmel_serial.c +++ b/drivers/serial/atmel_serial.c @@ -73,35 +73,35 @@ #define ATMEL_ISR_PASS_LIMIT 256 -#define UART_PUT_CR(port,v) writel(v, (port)->membase + ATMEL_US_CR) -#define UART_GET_MR(port) readl((port)->membase + ATMEL_US_MR) -#define UART_PUT_MR(port,v) writel(v, (port)->membase + ATMEL_US_MR) -#define UART_PUT_IER(port,v) writel(v, (port)->membase + ATMEL_US_IER) -#define UART_PUT_IDR(port,v) writel(v, (port)->membase + ATMEL_US_IDR) -#define UART_GET_IMR(port) readl((port)->membase + ATMEL_US_IMR) -#define UART_GET_CSR(port) readl((port)->membase + ATMEL_US_CSR) -#define UART_GET_CHAR(port) readl((port)->membase + ATMEL_US_RHR) -#define UART_PUT_CHAR(port,v) writel(v, (port)->membase + ATMEL_US_THR) -#define UART_GET_BRGR(port) readl((port)->membase + ATMEL_US_BRGR) -#define UART_PUT_BRGR(port,v) writel(v, (port)->membase + ATMEL_US_BRGR) -#define UART_PUT_RTOR(port,v) writel(v, (port)->membase + ATMEL_US_RTOR) - -// #define UART_GET_CR(port) readl((port)->membase + ATMEL_US_CR) // is write-only +#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) +#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) +#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) +#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) +#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) +#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) +#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) +#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) +#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) +#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) +#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) +#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) + +// #define UART_GET_CR(port) __raw_readl((port)->membase + ATMEL_US_CR) // is write-only /* PDC registers */ -#define UART_PUT_PTCR(port,v) writel(v, (port)->membase + ATMEL_PDC_PTCR) -#define UART_GET_PTSR(port) readl((port)->membase + ATMEL_PDC_PTSR) - -#define UART_PUT_RPR(port,v) writel(v, (port)->membase + ATMEL_PDC_RPR) -#define UART_GET_RPR(port) readl((port)->membase + ATMEL_PDC_RPR) -#define UART_PUT_RCR(port,v) writel(v, (port)->membase + ATMEL_PDC_RCR) -#define UART_PUT_RNPR(port,v) writel(v, (port)->membase + ATMEL_PDC_RNPR) -#define UART_PUT_RNCR(port,v) writel(v, (port)->membase + ATMEL_PDC_RNCR) - -#define UART_PUT_TPR(port,v) writel(v, (port)->membase + ATMEL_PDC_TPR) -#define UART_PUT_TCR(port,v) writel(v, (port)->membase + ATMEL_PDC_TCR) -//#define UART_PUT_TNPR(port,v) writel(v, (port)->membase + ATMEL_PDC_TNPR) -//#define UART_PUT_TNCR(port,v) writel(v, (port)->membase + ATMEL_PDC_TNCR) +#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) +#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) + +#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) +#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) +#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) +#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) +#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) + +#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) +#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) +//#define UART_PUT_TNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNPR) +//#define UART_PUT_TNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNCR) static int (*atmel_open_hook)(struct uart_port *); static void (*atmel_close_hook)(struct uart_port *); |
