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| author | Don Brace <don.brace@pmcs.com> | 2015-01-23 16:41:25 -0600 |
|---|---|---|
| committer | James Bottomley <JBottomley@Parallels.com> | 2015-02-02 09:57:35 -0800 |
| commit | 2662cab8984f6075e72e0997065c75ad3def6c95 (patch) | |
| tree | da70f7a7b0dbd25349b91ee3c0debe8a9b0b1ff9 /drivers/scsi | |
| parent | 3b747298786355c6934b0892fc9ae4ca44105192 (diff) | |
| download | op-kernel-dev-2662cab8984f6075e72e0997065c75ad3def6c95.zip op-kernel-dev-2662cab8984f6075e72e0997065c75ad3def6c95.tar.gz | |
hpsa: change how SA controllers are reset
Change how SA controllers are reset by changing PCI power levels.
The hpsa driver was finding the PCI_PM_CTRL_STATE_MASK offset
then reading/writing a bitmask to change the power state. There
are kernel functions that do the same operations. Better to use
the kernel functions.
Signed-off-by: Don Brace <don.brace@pmcs.com>
Reviewed-by: Scott Teel <scott.teel@pmcs.com>
Reviewed-by: Webb Scales <webbnh@hp.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Diffstat (limited to 'drivers/scsi')
| -rw-r--r-- | drivers/scsi/hpsa.c | 28 |
1 files changed, 10 insertions, 18 deletions
diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c index 9edacff..371d0a8 100644 --- a/drivers/scsi/hpsa.c +++ b/drivers/scsi/hpsa.c @@ -5689,30 +5689,22 @@ static int hpsa_controller_hard_reset(struct pci_dev *pdev, * the controller, place the interface device in D3 then to D0, * this causes a secondary PCI reset which will reset the * controller." */ - int pos; - u16 pmcsr; - - pos = pci_find_capability(pdev, PCI_CAP_ID_PM); - if (pos == 0) { - dev_err(&pdev->dev, - "hpsa_reset_controller: " - "PCI PM not supported\n"); - return -ENODEV; - } + + int rc = 0; + dev_info(&pdev->dev, "using PCI PM to reset controller\n"); + /* enter the D3hot power management state */ - pci_read_config_word(pdev, pos + PCI_PM_CTRL, - (__force u16 *)&pmcsr); - pmcsr &= ~PCI_PM_CTRL_STATE_MASK; - pmcsr |= (__force u16) PCI_D3hot; - pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr); + rc = pci_set_power_state(pdev, PCI_D3hot); + if (rc) + return rc; msleep(500); /* enter the D0 power management state */ - pmcsr &= ~PCI_PM_CTRL_STATE_MASK; - pmcsr |= (__force u16) PCI_D0; - pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr); + rc = pci_set_power_state(pdev, PCI_D0); + if (rc) + return rc; /* * The P600 requires a small delay when changing states. |
