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| author | Alim Akhtar <alim.akhtar@samsung.com> | 2018-05-06 15:44:16 +0530 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2018-05-18 10:44:52 -0400 |
| commit | 5ac6abc9415c3c70040b529631426b78e26108c4 (patch) | |
| tree | bc8d99a4405158d9d8aa8ca6e5c5045ffe53b888 /drivers/scsi/ufs | |
| parent | 1399c5b02c568700ba50ce1ec19c12e71b25c73d (diff) | |
| download | op-kernel-dev-5ac6abc9415c3c70040b529631426b78e26108c4.zip op-kernel-dev-5ac6abc9415c3c70040b529631426b78e26108c4.tar.gz | |
scsi: ufs: add quirk to disallow reset of interrupt aggregation
Some host controllers support interrupt aggregation but don't allow
resetting counter and timer in software.
Signed-off-by: Seungwon Jeon <essuuj@gmail.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/ufs')
| -rw-r--r-- | drivers/scsi/ufs/ufshcd.c | 3 | ||||
| -rw-r--r-- | drivers/scsi/ufs/ufshcd.h | 6 |
2 files changed, 8 insertions, 1 deletions
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 937355b..1ef4d46 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -4659,7 +4659,8 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba) * false interrupt if device completes another request after resetting * aggregation and before reading the DB. */ - if (ufshcd_is_intr_aggr_allowed(hba)) + if (ufshcd_is_intr_aggr_allowed(hba) && + !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) ufshcd_reset_intr_aggr(hba); tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index 09c285f..d8c922d 100644 --- a/drivers/scsi/ufs/ufshcd.h +++ b/drivers/scsi/ufs/ufshcd.h @@ -600,6 +600,12 @@ struct ufs_hba { */ #define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR 0x100 + /* + * This quirk needs to be enabled if host controller doesn't allow + * that the interrupt aggregation timer and counter are reset by s/w. + */ + #define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR 0x200 + unsigned int quirks; /* Deviations from standard UFSHCI spec. */ /* Device deviations from standard UFS device spec. */ |
