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authorKan Liang <kan.liang@intel.com>2015-04-21 05:34:41 -0400
committerIngo Molnar <mingo@kernel.org>2015-05-08 11:59:41 +0200
commit6d374056354a742eed4d0050498101e56e794c4b (patch)
treef03f738d250802781de0f3f84fc297e3b7694bf4 /drivers/scsi/scsi_logging.c
parent8b10c5e2b59ef2a80a07ab594a3b4987a4676211 (diff)
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perf/x86/intel: Fix SLM cache event list
iTLB-load-misses and LLC-load-misses count incorrectly on SLM. There is no ITLB.MISSES support on SLM. Event PAGE_WALKS.I_SIDE_WALK should be used to count iTLB-load-misses. This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks. DMND_DATA_RD counts both demand and DCU prefetch data reads. However, LLC-load-misses should only count demand reads. There is no way to not include prefetches with a single counter on SLM. So the LLC-load-misses support should be removed on SLM. Signed-off-by: Kan Liang <kan.liang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Borislav Petkov <bp@alien8.de> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1429608881-5055-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'drivers/scsi/scsi_logging.c')
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