mpt3sas: Added Combined Reply Queue feature to extend up-to 96 MSIX vector support

In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs to
up-to 96.

Following are changes that are done in this patch

1. This feature is enabled only for SAS3 C0 and higher revision cards and also
only when reply post free queue count is greater than 8.

2. To support this feature 12 SupplementalReplyPostHostIndex system interfaces
are used. MSI-X index numbered from 0 to 7 use the first
SupplementalReplyPostHostIndex system interface to update its corresponding
ReplyPostHostIndex values, MSI-X index numbered from 8 to 15 will use the
second SupplementalReplyPostHostIndex system interface and so on. These 12
SuppementalReplyPostHostIndex system interfaces address are saved in the array
replyPostRegisterIndex[].

3. As each SupplementalReplyPostHostIndex register supports 8 MSI-X
vectors. So MSIxIndex field in these register must contain a value between 0
and 7.

4. After processing the reply descriptors from a reply post free queues then
update the new reply post host index value in ReplyPostHostIndex field and
(msix_index mod 8) value in MSIxIndex field of SupplementalReplyPostHostIndex
register. The Address of this SupplementalReplyPostHostIndex register is
retrived from (msix_index/8)th entry of replyPostRegisterIndex[] array.

Signed-off-by: Sreekanth Reddy <Sreekanth.Reddy@avagotech.com>
Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com>
Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de>
Signed-off-by: James Bottomley <JBottomley@Odin.com>

1 files changed, 13 insertions, 1 deletions

diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h
index afa8816..a7386ee 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.h
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.h
@@ -158,6 +158,13 @@
 #define MPT3_DIAG_BUFFER_IS_RELEASED	(0x02)
 #define MPT3_DIAG_BUFFER_IS_DIAG_RESET	(0x04)
 
+/*
+ * Combined Reply Queue constants,
+ * There are twelve Supplemental Reply Post Host Index Registers
+ * and each register is at offset 0x10 bytes from the previous one.
+ */
+#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT 12
+#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET (0x10)
 
 /* OEM Identifiers */
 #define MFG10_OEM_ID_INVALID                   (0x00000000)
@@ -728,7 +735,8 @@ typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc);
  *				is assigned only ones
  * @reply_queue_count: number of reply queue's
  * @reply_queue_list: link list contaning the reply queue info
- * @reply_post_host_index: head index in the pool where FW completes IO
+ * @msix96_vector: 96 MSI-X vector support
+ * @replyPostRegisterIndex: index of next position in Reply Desc Post Queue
  * @delayed_tr_list: target reset link list
  * @delayed_tr_volume_list: volume target reset link list
  * @@temp_sensors_count: flag to carry the number of temperature sensors
@@ -937,6 +945,10 @@ struct MPT3SAS_ADAPTER {
 	u8		reply_queue_count;
 	struct list_head reply_queue_list;
 
+	u8		msix96_vector;
+	/* reply post register index */
+	resource_size_t	**replyPostRegisterIndex;
+
 	struct list_head delayed_tr_list;
 	struct list_head delayed_tr_volume_list;
 	u8		temp_sensors_count;