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authorAlexandre Belloni <alexandre.belloni@free-electrons.com>2015-05-25 15:19:55 +0200
committerThierry Reding <thierry.reding@gmail.com>2015-06-12 11:12:20 +0200
commit4c027f7ba8520df088d34ae045205a6f8e2a1d76 (patch)
tree2858c9721a8a1419c19aa24dfd74965cbc9732ff /drivers/pwm
parentcccb94543c8299e0bc7564cc6f8b26e0f15bafde (diff)
downloadop-kernel-dev-4c027f7ba8520df088d34ae045205a6f8e2a1d76.zip
op-kernel-dev-4c027f7ba8520df088d34ae045205a6f8e2a1d76.tar.gz
pwm: atmel: Fix incorrect CDTY value after enabling
CUPD is not flushed before enabling the channel so it will update CDTY/CPRD just after one period. So we always set CUPD, even when the channel is not enabled. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm')
-rw-r--r--drivers/pwm/pwm-atmel.c35
1 files changed, 18 insertions, 17 deletions
diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index d3c22de..89f9ca4 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -155,24 +155,25 @@ static void atmel_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
unsigned int val;
- if (test_bit(PWMF_ENABLED, &pwm->flags)) {
- /*
- * If the PWM channel is enabled, using the update register,
- * it needs to set bit 10 of CMR to 0
- */
- atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty);
- val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
- val &= ~PWM_CMR_UPD_CDTY;
- atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
- } else {
- /*
- * If the PWM channel is disabled, write value to duty and
- * period registers directly.
- */
- atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty);
- atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd);
- }
+ atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty);
+
+ val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
+ val &= ~PWM_CMR_UPD_CDTY;
+ atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
+
+ /*
+ * If the PWM channel is enabled, only update CDTY by using the update
+ * register, it needs to set bit 10 of CMR to 0
+ */
+ if (test_bit(PWMF_ENABLED, &pwm->flags))
+ return;
+ /*
+ * If the PWM channel is disabled, write value to duty and period
+ * registers directly.
+ */
+ atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty);
+ atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd);
}
static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
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