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| author | Alexandre Belloni <alexandre.belloni@free-electrons.com> | 2014-03-14 15:19:08 +0100 |
|---|---|---|
| committer | Thierry Reding <thierry.reding@gmail.com> | 2014-03-18 20:47:31 +0100 |
| commit | 8db9e29fe540c9640ea60f37ecf99d3a73bd12c5 (patch) | |
| tree | d7458bb791e71432ad12fe47aa9380d78830733f /drivers/pwm | |
| parent | 42586315b7b6e682bd4136a1a2bc2b1d50113487 (diff) | |
| download | op-kernel-dev-8db9e29fe540c9640ea60f37ecf99d3a73bd12c5.zip op-kernel-dev-8db9e29fe540c9640ea60f37ecf99d3a73bd12c5.tar.gz | |
pwm: atmel: Fix polarity handling
When atmel_pwm_config() calculates and then sets the prescaler, it is
overwriting the channel's CMR register so we are losing the CPOL
configuration.
As atmel_pwm_config() is always called before enabling a channel,
inverting the polarity doesn't work.
Fix that by reading CMR first and only overwriting the prescaler bits.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm')
| -rw-r--r-- | drivers/pwm/pwm-atmel.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index bf4144a..2d69e9c 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -32,6 +32,7 @@ /* Bit field in CMR */ #define PWM_CMR_CPOL (1 << 9) #define PWM_CMR_UPD_CDTY (1 << 10) +#define PWM_CMR_CPRE_MSK 0xF /* The following registers for PWM v1 */ #define PWMV1_CDTY 0x04 @@ -104,6 +105,7 @@ static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, unsigned long clk_rate, prd, dty; unsigned long long div; unsigned int pres = 0; + u32 val; int ret; if (test_bit(PWMF_ENABLED, &pwm->flags) && (period_ns != pwm->period)) { @@ -139,7 +141,10 @@ static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, return ret; } - atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, pres); + /* It is necessary to preserve CPOL, inside CMR */ + val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); + val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK); + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); atmel_pwm->config(chip, pwm, dty, prd); clk_disable(atmel_pwm->clk); |
