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authorVictor(Weiguo) Pan <wpan@nvidia.com>2016-06-22 17:17:20 +0530
committerThierry Reding <thierry.reding@gmail.com>2016-07-11 12:49:32 +0200
commite0ee1a75f412cc9f3b16127742a30baf975ec51f (patch)
treedfb4824aa4c49facba20717dfaeb765491e4f4f7 /drivers/pwm/pwm-tegra.c
parent5dfbd2bd5439f1ada5ddaa3883e9e038de5d2abe (diff)
downloadop-kernel-dev-e0ee1a75f412cc9f3b16127742a30baf975ec51f.zip
op-kernel-dev-e0ee1a75f412cc9f3b16127742a30baf975ec51f.tar.gz
pwm: tegra: Allow 100 % duty cycle
To get 100 % duty cycle (always high), pulse width needs to be set to 256. Signed-off-by: Victor(Weiguo) Pan <wpan@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm/pwm-tegra.c')
-rw-r--r--drivers/pwm/pwm-tegra.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 097658e..2026eaa 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -77,7 +77,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
* nearest integer during division.
*/
- c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
+ c = duty_ns * (1 << PWM_DUTY_WIDTH) + period_ns / 2;
do_div(c, period_ns);
val = (u32)c << PWM_DUTY_SHIFT;
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