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authorNishanth Menon <nm@ti.com>2013-05-30 13:08:34 +0300
committerKevin Hilman <khilman@linaro.org>2013-06-10 10:35:17 -0700
commitefe4e06de34953888504f4ea1d36c86db2267ea9 (patch)
treefb46c8250dba0d8a8f88571b3ef04f102ca370aa /drivers/power
parent317ddd256b9c24b0d78fa8018f80f1e495481a10 (diff)
downloadop-kernel-dev-efe4e06de34953888504f4ea1d36c86db2267ea9.zip
op-kernel-dev-efe4e06de34953888504f4ea1d36c86db2267ea9.tar.gz
PM / AVS: SmartReflex: disable errgen before vpbound disable
vpboundsintr_en is available inside the IP block as an re-sycned version and one which is not. Due to this, there is an 1 sysclk cycle window where the SR_SInterruptz signal could be asserted low. IF, intr_en is cleared on the exact same cycle as the irqclr, an additional pulse is generated which indicates for VP that an additional adjustment of voltage is required. This results in VP doing two voltage adjustments for the SRERR (based on configuration, upto 4 steps), instead of the needed 1 step. Due to the unexpected pulse from AVS which breaks the AVS-VP communication protocol, VP also ends up in a stuck condition by entering a state where VP module remains non-responsive to any futher AVS adjustment events. This creates the symptom called "TRANXDONE Timeout" scenario. By disabling errgen prior to disable of intr_en, this situation can be avoided. Signed-off-by: Vincent Bour <v-bour@ti.com> Signed-off-by: Leonardo Affortunati <l-affortunati@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrii.Tseglytskyi <andrii.tseglytskyi@ti.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
Diffstat (limited to 'drivers/power')
-rw-r--r--drivers/power/avs/smartreflex.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 6b2238b..f34d34d 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -449,12 +449,17 @@ int sr_disable_errgen(struct voltagedomain *voltdm)
return -EINVAL;
}
- /* Disable the interrupts of ERROR module */
- sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0);
-
/* Disable the Sensor and errorgen */
sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0);
+ /*
+ * Disable the interrupts of ERROR module
+ * NOTE: modify is a read, modify,write - an implicit OCP barrier
+ * which is required is present here - sequencing is critical
+ * at this point (after errgen is disabled, vpboundint disable)
+ */
+ sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0);
+
return 0;
}
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