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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-05-31 17:05:14 +0900 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2016-05-31 12:46:18 +0200 |
| commit | 72e5706aa786f6640b229717b7d9d537058c59cf (patch) | |
| tree | 8e14a67f1e887411ac0dbdcd5daa139b18eeb3c4 /drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | |
| parent | 9eaa98a63c8a34a807ba95e384aacd28fa60ddd9 (diff) | |
| download | op-kernel-dev-72e5706aa786f6640b229717b7d9d537058c59cf.zip op-kernel-dev-72e5706aa786f6640b229717b7d9d537058c59cf.tar.gz | |
pinctrl: uniphier: support 3-bit drive strength control
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive
strength control. Drive strength of some pins are controlled by
3-bit width registers (8-level granularity).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/uniphier/pinctrl-uniphier-core.c')
| -rw-r--r-- | drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index 7f7274e..017b84f 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -94,6 +94,9 @@ static void uniphier_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, case UNIPHIER_PIN_DRV_2BIT: drv_type = "8/12/16/20(mA)"; break; + case UNIPHIER_PIN_DRV_3BIT: + drv_type = "4/5/7/9/11/12/14/16(mA)"; + break; case UNIPHIER_PIN_DRV_FIXED4: drv_type = "4(mA)"; break; @@ -184,6 +187,7 @@ static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev, uniphier_pin_get_drv_type(pin->drv_data); const unsigned int strength_1bit[] = {4, 8}; const unsigned int strength_2bit[] = {8, 12, 16, 20}; + const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14, 16}; const unsigned int *supported_strength; unsigned int drvctrl, reg, shift, mask, width, val; int ret; @@ -191,12 +195,19 @@ static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev, switch (type) { case UNIPHIER_PIN_DRV_1BIT: supported_strength = strength_1bit; + reg = UNIPHIER_PINCTRL_DRVCTRL_BASE; width = 1; break; case UNIPHIER_PIN_DRV_2BIT: supported_strength = strength_2bit; + reg = UNIPHIER_PINCTRL_DRV2CTRL_BASE; width = 2; break; + case UNIPHIER_PIN_DRV_3BIT: + supported_strength = strength_3bit; + reg = UNIPHIER_PINCTRL_DRV3CTRL_BASE; + width = 4; + break; case UNIPHIER_PIN_DRV_FIXED4: *strength = 4; return 0; @@ -214,9 +225,6 @@ static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev, drvctrl = uniphier_pin_get_drvctrl(pin->drv_data); drvctrl *= width; - reg = (width == 2) ? UNIPHIER_PINCTRL_DRV2CTRL_BASE : - UNIPHIER_PINCTRL_DRVCTRL_BASE; - reg += drvctrl / 32 * 4; shift = drvctrl % 32; mask = (1U << width) - 1; @@ -368,18 +376,26 @@ static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev, uniphier_pin_get_drv_type(pin->drv_data); const unsigned int strength_1bit[] = {4, 8, -1}; const unsigned int strength_2bit[] = {8, 12, 16, 20, -1}; + const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14, 16, -1}; const unsigned int *supported_strength; unsigned int drvctrl, reg, shift, mask, width, val; switch (type) { case UNIPHIER_PIN_DRV_1BIT: supported_strength = strength_1bit; + reg = UNIPHIER_PINCTRL_DRVCTRL_BASE; width = 1; break; case UNIPHIER_PIN_DRV_2BIT: supported_strength = strength_2bit; + reg = UNIPHIER_PINCTRL_DRV2CTRL_BASE; width = 2; break; + case UNIPHIER_PIN_DRV_3BIT: + supported_strength = strength_3bit; + reg = UNIPHIER_PINCTRL_DRV3CTRL_BASE; + width = 4; + break; default: dev_err(pctldev->dev, "cannot change drive strength for pin %u (%s)\n", @@ -404,9 +420,6 @@ static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev, drvctrl = uniphier_pin_get_drvctrl(pin->drv_data); drvctrl *= width; - reg = (width == 2) ? UNIPHIER_PINCTRL_DRV2CTRL_BASE : - UNIPHIER_PINCTRL_DRVCTRL_BASE; - reg += drvctrl / 32 * 4; shift = drvctrl % 32; mask = (1U << width) - 1; |
