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| author | Chao Xie <chao.xie@marvell.com> | 2014-01-28 15:20:44 +0800 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2014-02-10 10:13:08 +0100 |
| commit | 4bd7547756af5c71d55e4d77f41db3d06c18b3e0 (patch) | |
| tree | a6806ff2060fd5f3b9d52753ab56884079f46e47 /drivers/pinctrl/sirf | |
| parent | b81e57e6ac35242ba59206b303ba6c7585764ee1 (diff) | |
| download | op-kernel-dev-4bd7547756af5c71d55e4d77f41db3d06c18b3e0.zip op-kernel-dev-4bd7547756af5c71d55e4d77f41db3d06c18b3e0.tar.gz | |
pinctrl: single: add low power mode support
For some silicons, the pin configuration register can control
the output of the pin when the pad including the pin enter
low power mode.
For example, the pin can be "Drive 1", "Drive 0", "Float" when
the pad including the pin enter low power mode.
It is very useful when you want to control the power leakeage
when the SOC enter low power mode, and can save more power for
the low power mode.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/sirf')
0 files changed, 0 insertions, 0 deletions
