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authorLinus Walleij <linus.walleij@linaro.org>2013-01-07 14:54:39 +0100
committerLinus Walleij <linus.walleij@linaro.org>2013-01-11 21:49:20 +0100
commitaa6e379aef84711f432ce754bda8e88b0270061c (patch)
treedc0002c57c26e4602a6239a973a0438ada8df159 /drivers/pinctrl/pinctrl-nomadik.c
parent483f33f63c1cb3c6becb465bac7b75d7ff5e3b8f (diff)
downloadop-kernel-dev-aa6e379aef84711f432ce754bda8e88b0270061c.zip
op-kernel-dev-aa6e379aef84711f432ce754bda8e88b0270061c.tar.gz
pinctrl/nomadik: make independent of <mach/irqs.h>
Some leftovers in the driver were using NOMADIK_* macros to translate the irq numbers to offsets, while the first base IRQ was already being passed from platform data, and the function setting the disable mask could just as well use the irqdomain. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-nomadik.c')
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 5d8a006..4814d54 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -32,7 +32,6 @@
#include <linux/pinctrl/consumer.h>
#include <linux/platform_data/pinctrl-nomadik.h>
#include <asm/mach/irq.h>
-#include <mach/irqs.h>
#include "pinctrl-nomadik.h"
#include "core.h"
@@ -217,7 +216,7 @@ nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
u32 falling = nmk_chip->fimsc & BIT(offset);
u32 rising = nmk_chip->rimsc & BIT(offset);
int gpio = nmk_chip->chip.base + offset;
- int irq = NOMADIK_GPIO_TO_IRQ(gpio);
+ int irq = irq_find_mapping(nmk_chip->domain, offset);
struct irq_data *d = irq_get_irq_data(irq);
if (!rising && !falling)
@@ -1428,7 +1427,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
platform_set_drvdata(dev, nmk_chip);
if (!np)
- irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio);
+ irq_start = pdata->first_irq;
nmk_chip->domain = irq_domain_add_simple(np,
NMK_GPIO_PER_CHIP, irq_start,
&nmk_gpio_irq_simple_ops, nmk_chip);
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