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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2016-06-23 13:49:36 +0300
committerLinus Walleij <linus.walleij@linaro.org>2016-06-29 09:59:35 +0200
commit4e80c8f505741cbdef3e10862ea36057e8d85e7c (patch)
tree0be7bbd8d0782de936659baab556ef7b53ce4494 /drivers/pinctrl/intel/Kconfig
parent11884b18ef0642e08f8a413e55c11d1cd6c62fee (diff)
downloadop-kernel-dev-4e80c8f505741cbdef3e10862ea36057e8d85e7c.zip
op-kernel-dev-4e80c8f505741cbdef3e10862ea36057e8d85e7c.tar.gz
pinctrl: intel: Add Intel Merrifield pin controller support
This driver adds pinctrl support for Intel Merrifield. The IP block which is called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver (gpio-intel-mid.c) will be updated accordingly to support pinctrl interface. Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/intel/Kconfig')
-rw-r--r--drivers/pinctrl/intel/Kconfig11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index 1c74e03..00fb055 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -29,6 +29,17 @@ config PINCTRL_CHERRYVIEW
Cherryview/Braswell pinctrl driver provides an interface that
allows configuring of SoC pins and using them as GPIOs.
+config PINCTRL_MERRIFIELD
+ tristate "Intel Merrifield pinctrl driver"
+ depends on X86_INTEL_MID
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ help
+ Merrifield Family-Level Interface Shim (FLIS) driver provides an
+ interface that allows configuring of SoC pins and using them as
+ GPIOs.
+
config PINCTRL_INTEL
tristate
select PINMUX
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