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authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>2015-04-02 17:01:11 +0900
committerKishon Vijay Abraham I <kishon@ti.com>2015-05-12 20:57:19 +0530
commita3ac3d4a296ac88578c3a982d044e53284d85344 (patch)
tree2a1a41ce7364ae7eed85514409732c97f6bb15d0 /drivers/phy
parent4581f798ec7373bea4530b7e57e6c6842f132bbd (diff)
downloadop-kernel-dev-a3ac3d4a296ac88578c3a982d044e53284d85344.zip
op-kernel-dev-a3ac3d4a296ac88578c3a982d044e53284d85344.tar.gz
phy: phy-rcar-gen2: Fix USBHS_UGSTS_LOCK value
According to the technical update (No. TN-RCS-B011A/E), the UGSTS LOCK bit location is bit 8, not bits 1 and 0. It also says that the register address offset of UGSTS is 0x88, not 0x90. So, this patch fixes the USBHS_UGSTS_LOCK value and some comments. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy')
-rw-r--r--drivers/phy/phy-rcar-gen2.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/phy/phy-rcar-gen2.c b/drivers/phy/phy-rcar-gen2.c
index 778276a..97d45f4 100644
--- a/drivers/phy/phy-rcar-gen2.c
+++ b/drivers/phy/phy-rcar-gen2.c
@@ -23,7 +23,7 @@
#define USBHS_LPSTS 0x02
#define USBHS_UGCTRL 0x80
#define USBHS_UGCTRL2 0x84
-#define USBHS_UGSTS 0x88 /* The manuals have 0x90 */
+#define USBHS_UGSTS 0x88 /* From technical update */
/* Low Power Status register (LPSTS) */
#define USBHS_LPSTS_SUSPM 0x4000
@@ -41,7 +41,7 @@
#define USBHS_UGCTRL2_USB0SEL_HS_USB 0x00000030
/* USB General status register (UGSTS) */
-#define USBHS_UGSTS_LOCK 0x00000300 /* The manuals have 0x3 */
+#define USBHS_UGSTS_LOCK 0x00000100 /* From technical update */
#define PHYS_PER_CHANNEL 2
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