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| author | Mohit Kumar <mohit.kumar@st.com> | 2014-04-14 14:22:54 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2014-04-16 10:20:48 -0600 |
| commit | 66c5c34bf80c28d370eb9bcf30153ea0304a288a (patch) | |
| tree | 170c490a116d3ab1301e1311a204b5fd463bf4a9 /drivers/pci | |
| parent | c9eaa447e77efe77b7fa4c953bd62de8297fd6c5 (diff) | |
| download | op-kernel-dev-66c5c34bf80c28d370eb9bcf30153ea0304a288a.zip op-kernel-dev-66c5c34bf80c28d370eb9bcf30153ea0304a288a.tar.gz | |
PCI: designware: Fix comment for setting number of lanes
Corrects comment for setting number of lanes.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 509a29d..8909e77 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -764,7 +764,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) u32 membase; u32 memlimit; - /* set the number of lines as 4 */ + /* set the number of lanes */ dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); val &= ~PORT_LINK_MODE_MASK; switch (pp->lanes) { |
