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authorGary Hade <garyhade@us.ibm.com>2007-10-03 15:56:30 -0700
committerGreg Kroah-Hartman <gregkh@suse.de>2007-10-12 15:03:18 -0700
commitfd64cb4606cbdd592b7119e82341d4ae5b56f2cc (patch)
tree7e7a6d9a3a2bbc29c2259351ccd315c7e666998b /drivers/pci
parent036fff4cf732c4d69f99a2915924935705744b00 (diff)
downloadop-kernel-dev-fd64cb4606cbdd592b7119e82341d4ae5b56f2cc.zip
op-kernel-dev-fd64cb4606cbdd592b7119e82341d4ae5b56f2cc.tar.gz
PCI: avoid P2P prefetch window for expansion ROMs
Avoid creating P2P prefetch window for expansion ROMs Because of the future possibility that P2P prefetch windows will contain address ranges above 4GB some BIOSes are providing space in the P2P non-prefetch windows for expansion ROMs. This is due to expansion ROM BAR 32-bit limitation. When expansion ROM BARs without BIOS assigned address(es) are currently found behind a P2P bridge, the kernel attempts to create a P2P prefetch window for them even though space for them has already been provided in the non-prefetch window. _CRS on some systems with certain resource conservation conscious BIOSes may not provide the extra 1MB or more memory resource needed for the expansion ROM motivated prefetch window causing resource allocation errors. This change corrects the problem by removing IORESOURCE_PREFETCH from the expansion ROM flags initialization. It also removes IORESOURCE_CACHEABLE which seems inappropriate if only non-cacheable memory is available. Signed-off-by: Gary Hade <gary.hade@us.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/probe.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 59d6c30..3112024 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -276,8 +276,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
if (sz) {
res->flags = (l & IORESOURCE_ROM_ENABLE) |
- IORESOURCE_MEM | IORESOURCE_PREFETCH |
- IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
+ IORESOURCE_MEM | IORESOURCE_READONLY;
res->start = l & PCI_ROM_ADDRESS_MASK;
res->end = res->start + (unsigned long) sz;
}
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