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authorNiklas Cassel <niklas.cassel@axis.com>2017-12-20 00:29:23 +0100
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2017-12-21 11:09:24 +0000
commit099a95f3591ade29da52131895a3ba9f92a0e82c (patch)
treea6c00c76e3d218edd8545e30c8587b82c1915b19 /drivers/pci
parent111111a72e677ff13d82d7b26c89a0cd84b32280 (diff)
downloadop-kernel-dev-099a95f3591ade29da52131895a3ba9f92a0e82c.zip
op-kernel-dev-099a95f3591ade29da52131895a3ba9f92a0e82c.tar.gz
PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits
Previously, dw_pcie_ep_set_msi() wrote all bits in the Message Control register, thus overwriting the PCI_MSI_FLAGS_64BIT bit. By clearing the PCI_MSI_FLAGS_64BIT bit, we break MSI on systems where the RC has set a 64 bit MSI address. Fix dw_pcie_ep_set_msi() so that it only sets MMC bits. Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/dwc/pcie-designware-ep.c4
-rw-r--r--drivers/pci/dwc/pcie-designware.h1
2 files changed, 4 insertions, 1 deletions
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
index d53d5f1..c92ab87 100644
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -220,7 +220,9 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
- val = (encode_int << MSI_CAP_MMC_SHIFT);
+ val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+ val &= ~MSI_CAP_MMC_MASK;
+ val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
return 0;
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index ecdede6..9aaf0cd 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -101,6 +101,7 @@
#define MSI_MESSAGE_CONTROL 0x52
#define MSI_CAP_MMC_SHIFT 1
+#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT)
#define MSI_CAP_MME_SHIFT 4
#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
#define MSI_MESSAGE_ADDR_L32 0x54
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