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| author | Yijing Wang <wangyijing@huawei.com> | 2015-05-21 15:05:04 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2015-05-29 15:35:26 -0500 |
| commit | 777e61ea40e4a94081b3123c76ea3fe977c368a2 (patch) | |
| tree | 69f6230aa9f5a8213f3bd0445d6c33251c906aec /drivers/pci/vc.c | |
| parent | c8fc9339409df88693742d323819ab8415cd2e9d (diff) | |
| download | op-kernel-dev-777e61ea40e4a94081b3123c76ea3fe977c368a2.zip op-kernel-dev-777e61ea40e4a94081b3123c76ea3fe977c368a2.tar.gz | |
PCI: Use dev->has_secondary_link to find downstream PCIe links
Previously we assumed that PCIe Root Ports and Downstream Ports had Links
on their secondary side. That is true in most systems, but it is possible
to connect a switch with either an Upstream or a Downstream Port leading
downstream.
Instead of relying on the component type to identify devices that have
links leading downstream, use the "dev->has_secondary_link" field.
[bhelgaas: changelog]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/vc.c')
| -rw-r--r-- | drivers/pci/vc.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/pci/vc.c b/drivers/pci/vc.c index 7e1304d..dfbab61 100644 --- a/drivers/pci/vc.c +++ b/drivers/pci/vc.c @@ -108,8 +108,7 @@ static void pci_vc_enable(struct pci_dev *dev, int pos, int res) struct pci_dev *link = NULL; /* Enable VCs from the downstream device */ - if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || - pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) + if (!dev->has_secondary_link) return; ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF); |
