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| author | Chris Metcalf <cmetcalf@tilera.com> | 2012-04-07 17:10:17 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2012-07-18 16:39:11 -0400 |
| commit | 129622672d70711c6c844fb529381ff0dad9085a (patch) | |
| tree | ea05d97ec3a457814e282c5cf8423c9e30994cb9 /drivers/pci/quirks.c | |
| parent | bce5bbbb23f780a792be7e594af7cd4b4aae1cd4 (diff) | |
| download | op-kernel-dev-129622672d70711c6c844fb529381ff0dad9085a.zip op-kernel-dev-129622672d70711c6c844fb529381ff0dad9085a.tar.gz | |
arch/tile: tilegx PCI root complex support
This change implements PCIe root complex support for tilegx using
the kernel support layer for accessing the TRIO hardware shim.
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> [changes in 07487f3]
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'drivers/pci/quirks.c')
| -rw-r--r-- | drivers/pci/quirks.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 194b243a..9478f72 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2143,9 +2143,9 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, quirk_unhide_mch_dev6); -#ifdef CONFIG_TILE +#ifdef CONFIG_TILEPRO /* - * The Tilera TILEmpower platform needs to set the link speed + * The Tilera TILEmpower tilepro platform needs to set the link speed * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe * capability register of the PEX8624 PCIe switch. The switch @@ -2160,7 +2160,7 @@ static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev) } } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); -#endif /* CONFIG_TILE */ +#endif /* CONFIG_TILEPRO */ #ifdef CONFIG_PCI_MSI /* Some chipsets do not support MSI. We cannot easily rely on setting |
