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authorJ. Bruce Fields <bfields@redhat.com>2010-12-17 13:29:07 -0500
committerJ. Bruce Fields <bfields@redhat.com>2010-12-17 13:29:07 -0500
commitec66ee3797e5848356cf593c6ec7aabf30a00cf1 (patch)
tree7ed5c84cc914644ffa1cd1b6a2b45db53fc224e8 /drivers/pci/quirks.c
parent1205065764f2eda3216ebe213143f69891ee3460 (diff)
parentb0c3844d8af6b9f3f18f31e1b0502fbefa2166be (diff)
downloadop-kernel-dev-ec66ee3797e5848356cf593c6ec7aabf30a00cf1.zip
op-kernel-dev-ec66ee3797e5848356cf593c6ec7aabf30a00cf1.tar.gz
Merge commit 'v2.6.37-rc6' into for-2.6.38
Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index f5c63fe..6f9350c 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2136,6 +2136,24 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
quirk_unhide_mch_dev6);
+#ifdef CONFIG_TILE
+/*
+ * The Tilera TILEmpower platform needs to set the link speed
+ * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
+ * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
+ * capability register of the PEX8624 PCIe switch. The switch
+ * supports link speed auto negotiation, but falsely sets
+ * the link speed to 5GT/s.
+ */
+static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
+{
+ if (tile_plx_gen1) {
+ pci_write_config_dword(dev, 0x98, 0x1);
+ mdelay(50);
+ }
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
+#endif /* CONFIG_TILE */
#ifdef CONFIG_PCI_MSI
/* Some chipsets do not support MSI. We cannot easily rely on setting
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