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authorYu Zhao <yu.zhao@intel.com>2009-03-20 11:25:12 +0800
committerJesse Barnes <jbarnes@virtuousgeek.org>2009-03-20 10:48:24 -0700
commit8c5cdb6adc6688b9b8fd82ea4a5cf4674dabad79 (patch)
tree79fbfde0cedf983b87cf6f782c108000d5c5752d /drivers/pci/iov.c
parentd1b054da8f599905f3c18a218961dcf17f9d5f13 (diff)
downloadop-kernel-dev-8c5cdb6adc6688b9b8fd82ea4a5cf4674dabad79.zip
op-kernel-dev-8c5cdb6adc6688b9b8fd82ea4a5cf4674dabad79.tar.gz
PCI: restore saved SR-IOV state
Restore the volatile registers in the SR-IOV capability after the D3->D0 transition. Reviewed-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci/iov.c')
-rw-r--r--drivers/pci/iov.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 66cc414..b121e47 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -129,6 +129,25 @@ static void sriov_release(struct pci_dev *dev)
dev->sriov = NULL;
}
+static void sriov_restore_state(struct pci_dev *dev)
+{
+ int i;
+ u16 ctrl;
+ struct pci_sriov *iov = dev->sriov;
+
+ pci_read_config_word(dev, iov->pos + PCI_SRIOV_CTRL, &ctrl);
+ if (ctrl & PCI_SRIOV_CTRL_VFE)
+ return;
+
+ for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++)
+ pci_update_resource(dev, i);
+
+ pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz);
+ pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
+ if (iov->ctrl & PCI_SRIOV_CTRL_VFE)
+ msleep(100);
+}
+
/**
* pci_iov_init - initialize the IOV capability
* @dev: the PCI device
@@ -180,3 +199,13 @@ int pci_iov_resource_bar(struct pci_dev *dev, int resno,
return dev->sriov->pos + PCI_SRIOV_BAR +
4 * (resno - PCI_IOV_RESOURCES);
}
+
+/**
+ * pci_restore_iov_state - restore the state of the IOV capability
+ * @dev: the PCI device
+ */
+void pci_restore_iov_state(struct pci_dev *dev)
+{
+ if (dev->is_physfn)
+ sriov_restore_state(dev);
+}
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