diff options
| author | Michael Chan <mchan@broadcom.com> | 2007-08-28 15:39:42 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2007-08-28 15:39:42 -0700 |
| commit | 594a9dfae7113d9601b2c353754c40d0b7e00a03 (patch) | |
| tree | dc9f35d62d17a8e18502de826b7f0af37b7a285a /drivers/net | |
| parent | 8e54588161577435d64dfb5cfdf40a73a5705ea0 (diff) | |
| download | op-kernel-dev-594a9dfae7113d9601b2c353754c40d0b7e00a03.zip op-kernel-dev-594a9dfae7113d9601b2c353754c40d0b7e00a03.tar.gz | |
[BNX2]: Add write posting comment.
Add comment to explain why we cannot read back after chip reset
before delaying.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/bnx2.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 0091860..854d80c 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c @@ -3934,6 +3934,10 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) /* Chip reset. */ REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); + /* Reading back any register after chip reset will hang the + * bus on 5706 A0 and A1. The msleep below provides plenty + * of margin for write posting. + */ if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || (CHIP_ID(bp) == CHIP_ID_5706_A1)) msleep(20); |
