diff options
| author | Miaoqing Pan <miaoqing@codeaurora.org> | 2016-02-18 17:20:02 +0800 |
|---|---|---|
| committer | Kalle Valo <kvalo@qca.qualcomm.com> | 2016-03-03 19:27:17 +0200 |
| commit | 25c0f301425cecdc51d7cc6eb4fb163d464236bc (patch) | |
| tree | fcb64ce2da8477649b6fbc773acc1cd053f7e40d /drivers/net/wireless | |
| parent | e9a26010f607621597f25e55d94faf85a2d0d5a4 (diff) | |
| download | op-kernel-dev-25c0f301425cecdc51d7cc6eb4fb163d464236bc.zip op-kernel-dev-25c0f301425cecdc51d7cc6eb4fb163d464236bc.tar.gz | |
ath9k: clear bb filter calibration power threshold
JP WiFi certification for bandwidth of channel 14 failed, the OBW
is lower than the requirement. Clear the bb filter calibration power
threshold to increase OBW(+2). The fix only for qca9531 chip now.
Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Diffstat (limited to 'drivers/net/wireless')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.c | 7 | ||||
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.h | 3 |
2 files changed, 9 insertions, 1 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index abd9646..06c1ca6 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c @@ -976,9 +976,14 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, /* * JAPAN regulatory. */ - if (chan->channel == 2484) + if (chan->channel == 2484) { ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); + if (AR_SREV_9531(ah)) + REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0, + AR_PHY_FLC_PWR_THRESH, 0); + } + ah->modes_index = modesIndex; ar9003_hw_override_ini(ah); ar9003_hw_set_channel_regs(ah, chan); diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h index c5f8bc4..566da78 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h @@ -487,6 +487,9 @@ #define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150) #define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158) +#define AR_PHY_FLC_PWR_THRESH 7 +#define AR_PHY_FLC_PWR_THRESH_S 0 + #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW 3 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S 0 |
