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| author | Eran Harary <eran.harary@intel.com> | 2014-01-23 16:26:32 +0200 |
|---|---|---|
| committer | Emmanuel Grumbach <emmanuel.grumbach@intel.com> | 2014-02-03 22:23:32 +0200 |
| commit | 189fa2faac49bce07c6c6d83eca21cbe5bf47411 (patch) | |
| tree | 359d94bf34ed99a36e201bc5f35190ec5ee9e1f5 /drivers/net/wireless/iwlwifi/iwl-csr.h | |
| parent | e4a9f8cea50406a57c8dc5429d9aca6429d82436 (diff) | |
| download | op-kernel-dev-189fa2faac49bce07c6c6d83eca21cbe5bf47411.zip op-kernel-dev-189fa2faac49bce07c6c6d83eca21cbe5bf47411.tar.gz | |
iwlwifi: pcie: fix secure section / dual cpu firmware loading
Also handle the bypass mode in which the second CPU doesn't
interfere.
Signed-off-by: Eran Harary <eran.harary@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-csr.h')
| -rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-csr.h | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h index 9d32551..f13dec9 100644 --- a/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/iwlwifi/iwl-csr.h @@ -395,38 +395,6 @@ #define CSR_DRAM_INT_TBL_ENABLE (1 << 31) #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) -/* SECURE boot registers */ -#define CSR_SECURE_BOOT_CONFIG_ADDR (0x100) -enum secure_boot_config_reg { - CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, - CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, -}; - -#define CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) -#define CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) -enum secure_boot_status_reg { - CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, - CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, - CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, - CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, - CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, -}; - -#define CSR_UCODE_LOAD_STATUS_ADDR (0x100) -enum secure_load_status_reg { - CSR_CPU_STATUS_LOADING_STARTED = 0x00000001, - CSR_CPU_STATUS_LOADING_COMPLETED = 0x00000002, - CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, - CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, -}; - -#define CSR_SECURE_INSPECTOR_CODE_ADDR (0x100) -#define CSR_SECURE_INSPECTOR_DATA_ADDR (0x100) - -#define CSR_SECURE_TIME_OUT (100) - -#define FH_TCSR_0_REG0 (0x1D00) - /* * HBUS (Host-side Bus) * |
