diff options
| author | Piotr Haber <phaber@broadcom.com> | 2013-04-11 13:28:46 +0200 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2013-04-12 14:27:53 -0400 |
| commit | 4a3da9906bbf37f6b0d44ddb753d3198e73c3c6d (patch) | |
| tree | ae399c6386c2db3412b30e15335f1515d894ee3e /drivers/net/wireless/brcm80211/include | |
| parent | fe29f54cd574eab7b521445419f355c0ecd995cc (diff) | |
| download | op-kernel-dev-4a3da9906bbf37f6b0d44ddb753d3198e73c3c6d.zip op-kernel-dev-4a3da9906bbf37f6b0d44ddb753d3198e73c3c6d.tar.gz | |
brcmfmac: support save&restore firmware feature
Save & restore is an advanced power saving feature,
supported only on selected devices.
SR operation is almost completely transparent to the driver.
Support for it is hardware and firmware dependent.
Reviewed-by: Hante Meuleman <meuleman@broadcom.com>
Reviewed-by: Arend van Spriel <arend@broadcom.com>
Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com>
Reviewed-by: Franky (Zhenhui) Lin <frankyl@broadcom.com>
Signed-off-by: Piotr Haber <phaber@broadcom.com>
Signed-off-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/brcm80211/include')
| -rw-r--r-- | drivers/net/wireless/brcm80211/include/chipcommon.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/net/wireless/brcm80211/include/chipcommon.h b/drivers/net/wireless/brcm80211/include/chipcommon.h index f96834a..d242333 100644 --- a/drivers/net/wireless/brcm80211/include/chipcommon.h +++ b/drivers/net/wireless/brcm80211/include/chipcommon.h @@ -205,7 +205,7 @@ struct chipcregs { u32 res_req_timer_sel; u32 res_req_timer; u32 res_req_mask; - u32 PAD; + u32 pmucapabilities_ext; /* 0x64c, pmurev >=15 */ u32 chipcontrol_addr; /* 0x650 */ u32 chipcontrol_data; /* 0x654 */ u32 regcontrol_addr; @@ -214,7 +214,11 @@ struct chipcregs { u32 pllcontrol_data; u32 pmustrapopt; /* 0x668, corerev >= 28 */ u32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ - u32 PAD[100]; + u32 retention_ctl; /* 0x670, pmurev >= 15 */ + u32 PAD[3]; + u32 retention_grpidx; /* 0x680 */ + u32 retention_grpctl; /* 0x684 */ + u32 PAD[94]; u16 sromotp[768]; }; @@ -276,6 +280,12 @@ struct chipcregs { #define PCAP5_VC_SHIFT 22 #define PCAP5_CC_MASK 0xf8000000 #define PCAP5_CC_SHIFT 27 +/* pmucapabilites_ext PMU rev >= 15 */ +#define PCAPEXT_SR_SUPPORTED_MASK (1 << 1) +/* retention_ctl PMU rev >= 15 */ +#define PMU_RCTL_MACPHY_DISABLE_MASK (1 << 26) +#define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27) + /* * Maximum delay for the PMU state transition in us. |
