diff options
| author | Rajkumar Manoharan <rmanoharan@atheros.com> | 2011-03-15 23:11:35 +0530 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2011-03-30 14:15:12 -0400 |
| commit | e7fc63388def06d2d1bdb6916748c92c037a42c6 (patch) | |
| tree | 120e3880e7fb2fb18398aaf1be4f7740f6a5d561 /drivers/net/wireless/ath/ath9k/hw.h | |
| parent | b0a9ede228175c25f76314a028d305fd5b2de427 (diff) | |
| download | op-kernel-dev-e7fc63388def06d2d1bdb6916748c92c037a42c6.zip op-kernel-dev-e7fc63388def06d2d1bdb6916748c92c037a42c6.tar.gz | |
ath9k_hw: Speedup register ops for HTC driver
Fine-tuning register write operation and avoid unnecessay
delays for ath9k_htc driver, saves hw reset time which
improves scanning time and also solves one of the following
scenario.
Sometimes the ACK is sent by STA for assoc response is not
seen at AP side. So the AP continues to send retry assoc
responses. At the STA side, since the assoc response was
already forwarded to mac80211, it proceeded to channel change
which in turns does chip reset.
In most of the cases the chip reset was completed before
max retries are reached at AP side. Hence STA can able to ACK
the retried frames again. But in clear environment these retries
are completed within shortspan of time.
Since ath9k_htc consumes more time for hw reset, this latency
is causing dissociation by AP due to max reties are reached.
This issue was originally reported with Cisco Aironet 1250 AP
in HT40 mode in noise free environment.
Signed-off-by: Rajkumar Manoharan <rmanoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.h')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index 6650fd4..c86eea2 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h @@ -99,18 +99,22 @@ #define REG_CLR_BIT(_a, _r, _f) \ REG_WRITE(_a, _r, REG_READ(_a, _r) & ~(_f)) -#define DO_DELAY(x) do { \ - if ((++(x) % 64) == 0) \ - udelay(1); \ +#define DO_DELAY(x) do { \ + if (((++(x) % 64) == 0) && \ + (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ + != ATH_USB)) \ + udelay(1); \ } while (0) #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ int r; \ + ENABLE_REGWRITE_BUFFER(ah); \ for (r = 0; r < ((iniarray)->ia_rows); r++) { \ REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ INI_RA((iniarray), r, (column))); \ DO_DELAY(regWr); \ } \ + REGWRITE_BUFFER_FLUSH(ah); \ } while (0) #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
