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| author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-06-17 13:16:10 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-06-17 18:46:45 -0700 |
| commit | fb1001f3de1a8576b25d929502f1fe7865ff32dc (patch) | |
| tree | afb9115df813d278e7747ccfc6c138464fe92a23 /drivers/net/ucc_geth.h | |
| parent | f3a32500ba8f3ec9ee0c12836fcfd315f1256db4 (diff) | |
| download | op-kernel-dev-fb1001f3de1a8576b25d929502f1fe7865ff32dc.zip op-kernel-dev-fb1001f3de1a8576b25d929502f1fe7865ff32dc.tar.gz | |
net/ucc_geth: Add SGMII support for UCC GETH driver
-- derived from reverted commit 047584ce94108012288554a5f84585d792cc7f8f
-- reworked by Grant Likely to play nice with commit:
"net: Rework ucc_geth driver to use of_mdio infrastructure"
(0b9da337dca972e7a4144e298ec3adb8f244d4a4)
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ucc_geth.h')
| -rw-r--r-- | drivers/net/ucc_geth.h | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h index dca628a..1525bf5 100644 --- a/drivers/net/ucc_geth.h +++ b/drivers/net/ucc_geth.h @@ -1,5 +1,5 @@ /* - * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. + * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved. * * Author: Shlomi Gridish <gridish@freescale.com> * @@ -193,6 +193,31 @@ struct ucc_geth { #define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */ #define ENET_TBI_MII_TBICON 0x11 /* TBI control */ +/* TBI MDIO register bit fields*/ +#define TBISR_LSTATUS 0x0004 +#define TBICON_CLK_SELECT 0x0020 +#define TBIANA_ASYMMETRIC_PAUSE 0x0100 +#define TBIANA_SYMMETRIC_PAUSE 0x0080 +#define TBIANA_HALF_DUPLEX 0x0040 +#define TBIANA_FULL_DUPLEX 0x0020 +#define TBICR_PHY_RESET 0x8000 +#define TBICR_ANEG_ENABLE 0x1000 +#define TBICR_RESTART_ANEG 0x0200 +#define TBICR_FULL_DUPLEX 0x0100 +#define TBICR_SPEED1_SET 0x0040 + +#define TBIANA_SETTINGS ( \ + TBIANA_ASYMMETRIC_PAUSE \ + | TBIANA_SYMMETRIC_PAUSE \ + | TBIANA_FULL_DUPLEX \ + ) +#define TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */ @@ -1100,6 +1125,7 @@ struct ucc_geth_info { u16 pausePeriod; u16 extensionField; struct device_node *phy_node; + struct device_node *tbi_node; u8 weightfactor[NUM_TX_QUEUES]; u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES]; u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX]; |
