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| author | Ben Hutchings <bhutchings@solarflare.com> | 2008-12-12 22:00:17 -0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2008-12-12 22:00:17 -0800 |
| commit | e6fa2eb789f49dc51a20d3db0d410bc8158abb43 (patch) | |
| tree | 4b61712a720b2f90b47fe69127a76f258e3322f8 /drivers/net/sfc/mdio_10g.h | |
| parent | 766ca0fa6bf1600bdf4bc7726c74f14c8455c6b8 (diff) | |
| download | op-kernel-dev-e6fa2eb789f49dc51a20d3db0d410bc8158abb43.zip op-kernel-dev-e6fa2eb789f49dc51a20d3db0d410bc8158abb43.tar.gz | |
sfc: Add support for Solarflare 10Xpress SFT9001
Add type codes for the new PHY and rename the SFX7101 type code.
Add definition of clause 22 extension MMD.
Adapt the 10Xpress SFX7101 code to support the SFT9001 as well.
Clean up register definitions.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sfc/mdio_10g.h')
| -rw-r--r-- | drivers/net/sfc/mdio_10g.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/sfc/mdio_10g.h b/drivers/net/sfc/mdio_10g.h index 80c63dd..4091182 100644 --- a/drivers/net/sfc/mdio_10g.h +++ b/drivers/net/sfc/mdio_10g.h @@ -33,6 +33,8 @@ #define MDIO_MMD_TC (6) /* Auto negotiation */ #define MDIO_MMD_AN (7) +/* Clause 22 extension */ +#define MDIO_MMD_C22EXT 29 /* Generic register locations */ #define MDIO_MMDREG_CTRL1 (0) @@ -82,6 +84,7 @@ #define MDIO_MMDREG_DEVS_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS) #define MDIO_MMDREG_DEVS_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD) #define MDIO_MMDREG_DEVS_AN DEV_PRESENT_BIT(MDIO_MMD_AN) +#define MDIO_MMDREG_DEVS_C22EXT DEV_PRESENT_BIT(MDIO_MMD_C22EXT) /* Bits in MMDREG_SPEED */ #define MDIO_MMDREG_SPEED_10G_LBN 0 @@ -125,6 +128,11 @@ #define MDIO_PMAPMD_CTRL2_10_BT (0xf) #define MDIO_PMAPMD_CTRL2_TYPE_MASK (0xf) +/* PMA 10GBT registers */ +#define MDIO_PMAPMD_10GBT_TXPWR (131) +#define MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN (0) +#define MDIO_PMAPMD_10GBT_TXPWR_SHORT_WIDTH (1) + /* PHY XGXS lane state */ #define MDIO_PHYXS_LANE_STATE (0x18) #define MDIO_PHYXS_LANE_ALIGNED_LBN (12) |
