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| author | Alexander Duyck <alexander.h.duyck@intel.com> | 2009-07-23 18:08:35 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-07-26 09:46:49 -0700 |
| commit | 009bc06e5311b48c77b7708d9e226ae0f110373a (patch) | |
| tree | fceeade485befdbda8047d14bb59c9c0b0b0dad8 /drivers/net/igb/e1000_defines.h | |
| parent | 12645a196eccb9209f88915f56a686086dea1a16 (diff) | |
| download | op-kernel-dev-009bc06e5311b48c77b7708d9e226ae0f110373a.zip op-kernel-dev-009bc06e5311b48c77b7708d9e226ae0f110373a.tar.gz | |
igb: add completion timeout workaround for 82575/82576
The 82575 and 82576 hardware can both experience data corruption issues if
a pci-e completion arrives after the timeout value. In order to avoid this
we need to increase the timeout value while pci-e master is disabled.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/igb/e1000_defines.h')
| -rw-r--r-- | drivers/net/igb/e1000_defines.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h index 3bda3db..c858293 100644 --- a/drivers/net/igb/e1000_defines.h +++ b/drivers/net/igb/e1000_defines.h @@ -435,6 +435,12 @@ /* Flow Control */ #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ +/* PCI Express Control */ +#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 +#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 +#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 +#define E1000_GCR_CAP_VER2 0x00040000 + /* PHY Control Register */ #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ @@ -569,9 +575,11 @@ /* PCI/PCI-X/PCI-EX Config space */ #define PCIE_LINK_STATUS 0x12 +#define PCIE_DEVICE_CONTROL2 0x28 #define PCIE_LINK_WIDTH_MASK 0x3F0 #define PCIE_LINK_WIDTH_SHIFT 4 +#define PCIE_DEVICE_CONTROL2_16ms 0x0005 #define PHY_REVISION_MASK 0xFFFFFFF0 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ |
