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authorEugene Surovegin <ebs@ebshome.net>2005-10-29 12:47:41 -0700
committerJeff Garzik <jgarzik@pobox.com>2005-10-29 18:06:54 -0400
commit86e7fe705d1b894df0cbb785991c92fa298af8fb (patch)
tree696caeca281ad23941a8a4bfeec96728273b5cb6 /drivers/net/ibm_emac
parent1b195916dd9111bbaf043d0dcfdc5d6908590c6e (diff)
downloadop-kernel-dev-86e7fe705d1b894df0cbb785991c92fa298af8fb.zip
op-kernel-dev-86e7fe705d1b894df0cbb785991c92fa298af8fb.tar.gz
[PATCH] PPC 4xx EMAC driver: fix VSC8201 PHY initialization
* MII registers must override strap pins * disable "echo" mode to make 10/HDX work (Franz Sirl) Signed-off-by: Eugene Surovegin <ebs@ebshome.net> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net/ibm_emac')
-rw-r--r--drivers/net/ibm_emac/ibm_emac_phy.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/net/ibm_emac/ibm_emac_phy.c b/drivers/net/ibm_emac/ibm_emac_phy.c
index a27e49c..67935dd 100644
--- a/drivers/net/ibm_emac/ibm_emac_phy.c
+++ b/drivers/net/ibm_emac/ibm_emac_phy.c
@@ -236,12 +236,16 @@ static struct mii_phy_def genmii_phy_def = {
};
/* CIS8201 */
+#define MII_CIS8201_10BTCSR 0x16
+#define TENBTCSR_ECHO_DISABLE 0x2000
#define MII_CIS8201_EPCR 0x17
#define EPCR_MODE_MASK 0x3000
#define EPCR_GMII_MODE 0x0000
#define EPCR_RGMII_MODE 0x1000
#define EPCR_TBI_MODE 0x2000
#define EPCR_RTBI_MODE 0x3000
+#define MII_CIS8201_ACSR 0x1c
+#define ACSR_PIN_PRIO_SELECT 0x0004
static int cis8201_init(struct mii_phy *phy)
{
@@ -269,6 +273,14 @@ static int cis8201_init(struct mii_phy *phy)
}
phy_write(phy, MII_CIS8201_EPCR, epcr);
+
+ /* MII regs override strap pins */
+ phy_write(phy, MII_CIS8201_ACSR,
+ phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
+
+ /* Disable TX_EN -> CRS echo mode, otherwise 10/HDX doesn't work */
+ phy_write(phy, MII_CIS8201_10BTCSR,
+ phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
return 0;
}
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