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authorMaciej W. Rozycki <macro@linux-mips.org>2014-09-25 11:06:45 +0100
committerDavid S. Miller <davem@davemloft.net>2014-09-28 17:22:09 -0400
commitb1a6d3ecf806457d3e76ac0044db424be3c9422d (patch)
treed0951a96258a0fd38b88f01bf56cbbb525fb0f4f /drivers/net/fddi
parent8a189f1288b654e45f2ec9393abfb1390b261ae9 (diff)
downloadop-kernel-dev-b1a6d3ecf806457d3e76ac0044db424be3c9422d.zip
op-kernel-dev-b1a6d3ecf806457d3e76ac0044db424be3c9422d.tar.gz
defxx: DEFEA's Burst Holdoff register initialization fix
Use the mask rather than bit number macro to initialize the chip select control bit for PDQ register space decoding in the Burst Holdoff register. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/fddi')
-rw-r--r--drivers/net/fddi/defxx.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/fddi/defxx.c b/drivers/net/fddi/defxx.c
index 6068db87..15a18fb 100644
--- a/drivers/net/fddi/defxx.c
+++ b/drivers/net/fddi/defxx.c
@@ -748,9 +748,9 @@ static void dfx_bus_init(struct net_device *dev)
*/
val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF);
if (dfx_use_mmio)
- val |= PI_BURST_HOLDOFF_V_MEM_MAP;
+ val |= PI_BURST_HOLDOFF_M_MEM_MAP;
else
- val &= ~PI_BURST_HOLDOFF_V_MEM_MAP;
+ val &= ~PI_BURST_HOLDOFF_M_MEM_MAP;
outb(val, base_addr + PI_DEFEA_K_BURST_HOLDOFF);
/* Enable interrupts at EISA bus interface chip (ESIC) */
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