diff options
| author | Giuseppe CAVALLARO <peppe.cavallaro@st.com> | 2012-04-04 04:33:26 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2012-04-04 18:39:24 -0400 |
| commit | 18f05d64ec36e27892cc0f55be707762aae053a1 (patch) | |
| tree | 2800ef8ec49ef318ffe16b93db4b15cebc1f39ca /drivers/net/ethernet/stmicro | |
| parent | ba1377ffe90a04d9a1d526067909d24e3cf7a3f7 (diff) | |
| download | op-kernel-dev-18f05d64ec36e27892cc0f55be707762aae053a1.zip op-kernel-dev-18f05d64ec36e27892cc0f55be707762aae053a1.tar.gz | |
stmmac: extend CSR Clock Range programming
The CSR Clock Range has been reworked and new macros has
been added in the platform header to allow the CSR Clock
Range selection in the GMII Address Register.
The previous work didn't add the other fields
that can be used to achieve MDC clock of frequency
higher than the IEEE 802.3 specified frequency limit
of 2.5 MHz and program a clock divider of lower value.
On such platforms, these are used indeed so this patch
adds them.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/stmicro')
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c index 83292f4..1a42014 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c @@ -70,7 +70,7 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) int data; u16 regValue = (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))); - regValue |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2); + regValue |= MII_BUSY | ((priv->plat->clk_csr & 0xF) << 2); if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) return -EBUSY; @@ -106,7 +106,7 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))) | MII_WRITE; - value |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2); + value |= MII_BUSY | ((priv->plat->clk_csr & 0xF) << 2); /* Wait until any existing MII operation is complete */ if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) |
