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| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2018-07-26 15:05:37 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-07-29 12:33:30 -0700 |
| commit | 9939a46d90c6c76f4533d534dbadfa7b39dc6acc (patch) | |
| tree | e8f9af52182bc85cf5af89556c393280320bb151 /drivers/net/ethernet/stmicro/stmmac | |
| parent | 383d470936c05554219094a4d364d964cb324827 (diff) | |
| download | op-kernel-dev-9939a46d90c6c76f4533d534dbadfa7b39dc6acc.zip op-kernel-dev-9939a46d90c6c76f4533d534dbadfa7b39dc6acc.tar.gz | |
NET: stmmac: align DMA stuff to largest cache line length
As for today STMMAC_ALIGN macro (which is used to align DMA stuff)
relies on L1 line length (L1_CACHE_BYTES).
This isn't correct in case of system with several cache levels
which might have L1 cache line length smaller than L2 line. This
can lead to sharing one cache line between DMA buffer and other
data, so we can lose this data while invalidate DMA buffer before
DMA transaction.
Fix that by using SMP_CACHE_BYTES instead of L1_CACHE_BYTES for
aligning.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac')
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 60f59ab..ef6a8d3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -53,7 +53,7 @@ #include "dwmac1000.h" #include "hwif.h" -#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) +#define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES) #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) /* Module parameters */ |
