diff options
| author | Carolyn Wyborny <carolyn.wyborny@intel.com> | 2012-11-22 02:49:22 +0000 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2012-12-01 03:20:40 -0800 |
| commit | 3860a0bf748bf98a30f2bab73d5e3653583f7b47 (patch) | |
| tree | f9dd8e6625a15b964038192be8f728c27ecd8f48 /drivers/net/ethernet/intel | |
| parent | a0483e2eb63d3b2f14a821edb21b3e610bfba5bd (diff) | |
| download | op-kernel-dev-3860a0bf748bf98a30f2bab73d5e3653583f7b47.zip op-kernel-dev-3860a0bf748bf98a30f2bab73d5e3653583f7b47.tar.gz | |
igb: Unset sigdetect for SERDES loopback on 82580 and i350
This patch unsets the sigdetect bit for SERDES loopback tests on 82580 and
i350 parts. The loopback test can fail on these parts without this
setting.
Signed-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel')
| -rw-r--r-- | drivers/net/ethernet/intel/igb/igb.h | 2 | ||||
| -rw-r--r-- | drivers/net/ethernet/intel/igb/igb_ethtool.c | 14 |
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/igb/igb.h b/drivers/net/ethernet/intel/igb/igb.h index c15a481..17f1686 100644 --- a/drivers/net/ethernet/intel/igb/igb.h +++ b/drivers/net/ethernet/intel/igb/igb.h @@ -42,6 +42,8 @@ struct igb_adapter; +#define E1000_PCS_CFG_IGN_SD 1 + /* Interrupt defines */ #define IGB_START_ITR 648 /* ~6000 ints/sec */ #define IGB_4K_ITR 980 diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c index e2288b5..bfe9208 100644 --- a/drivers/net/ethernet/intel/igb/igb_ethtool.c +++ b/drivers/net/ethernet/intel/igb/igb_ethtool.c @@ -1624,6 +1624,20 @@ static int igb_setup_loopback_test(struct igb_adapter *adapter) reg &= ~E1000_CONNSW_ENRGSRC; wr32(E1000_CONNSW, reg); + /* Unset sigdetect for SERDES loopback on + * 82580 and i350 devices. + */ + switch (hw->mac.type) { + case e1000_82580: + case e1000_i350: + reg = rd32(E1000_PCS_CFG0); + reg |= E1000_PCS_CFG_IGN_SD; + wr32(E1000_PCS_CFG0, reg); + break; + default: + break; + } + /* Set PCS register for forced speed */ reg = rd32(E1000_PCS_LCTL); reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ |
