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authorEmil Tantilov <emil.s.tantilov@intel.com>2017-12-11 10:37:04 -0800
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2018-01-26 07:46:50 -0800
commit16b359498b12e83b795be160f105d7c3dc4a8bb5 (patch)
tree18bae71f71d56385452547f95a512089cbd22d56 /drivers/net/ethernet/intel/ixgbevf/ixgbevf.h
parent24bff091d7691c162580bcdb57bb00015471d34e (diff)
downloadop-kernel-dev-16b359498b12e83b795be160f105d7c3dc4a8bb5.zip
op-kernel-dev-16b359498b12e83b795be160f105d7c3dc4a8bb5.tar.gz
ixgbevf: add support for DMA_ATTR_SKIP_CPU_SYNC/WEAK_ORDERING
Based on commit 5be5955425c2 ("igb: update driver to make use of DMA_ATTR_SKIP_CPU_SYNC") and commit 7bd175928280 ("igb: Add support for DMA_ATTR_WEAK_ORDERING") Convert the calls to dma_map/unmap_page() to the attributes version and add DMA_ATTR_SKIP_CPU_SYNC/WEAK_ORDERING which should help improve performance on some platforms. Move sync_for_cpu call before we perform a prefetch to avoid invalidating the first 128 bytes of the packet on architectures where that call may invalidate the cache. Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com> Tested-by: Krishneil Singh <krishneil.k.singh@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ixgbevf/ixgbevf.h')
-rw-r--r--drivers/net/ethernet/intel/ixgbevf/ixgbevf.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/ixgbevf/ixgbevf.h b/drivers/net/ethernet/intel/ixgbevf/ixgbevf.h
index 581f44b..b1da9f4 100644
--- a/drivers/net/ethernet/intel/ixgbevf/ixgbevf.h
+++ b/drivers/net/ethernet/intel/ixgbevf/ixgbevf.h
@@ -260,6 +260,9 @@ static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value)
#define MIN_MSIX_Q_VECTORS 1
#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
+#define IXGBEVF_RX_DMA_ATTR \
+ (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
+
/* board specific private data structure */
struct ixgbevf_adapter {
/* this field must be first, see ixgbevf_process_skb_fields */
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