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author | Alexander Duyck <alexander.h.duyck@intel.com> | 2014-01-15 17:38:41 -0800 |
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committer | David S. Miller <davem@davemloft.net> | 2014-01-15 21:48:18 -0800 |
commit | dbf231af81a789645f7c8d7e3ddce48e1ef08083 (patch) | |
tree | dc0cdd6a5e7d3f0b8628069a756e779ca0319803 /drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c | |
parent | 87397379d566d5d8692df1bfc22bef95fd64ae3b (diff) | |
download | op-kernel-dev-dbf231af81a789645f7c8d7e3ddce48e1ef08083.zip op-kernel-dev-dbf231af81a789645f7c8d7e3ddce48e1ef08083.tar.gz |
ixgbe: Clear head write-back registers on VF reset
The Tx head write-back registers are not cleared during an FLR or VF reset.
As a result a configuration that had head write-back enabled can leave the
registers set after the driver is unloaded. If the next driver loaded doesn't
use the write-back registers this can lead to a bad configuration where
head write-back is enabled, but the driver didn't request it.
To avoid this situation the PF should be resetting the Tx head write-back
registers when the VF requests a reset.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c')
-rw-r--r-- | drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c index 43e10c6..0558c71 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c @@ -698,6 +698,15 @@ static int ixgbe_vf_reset_msg(struct ixgbe_adapter *adapter, u32 vf) reg |= (1 << vf_shift); IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg); + /* + * Reset the VFs TDWBAL and TDWBAH registers + * which are not cleared by an FLR + */ + for (i = 0; i < q_per_pool; i++) { + IXGBE_WRITE_REG(hw, IXGBE_PVFTDWBAHn(q_per_pool, vf, i), 0); + IXGBE_WRITE_REG(hw, IXGBE_PVFTDWBALn(q_per_pool, vf, i), 0); + } + /* reply to reset with ack and vf mac address */ msgbuf[0] = IXGBE_VF_RESET; if (!is_zero_ether_addr(vf_mac)) { |