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| author | Alexander Duyck <alexander.h.duyck@intel.com> | 2017-01-17 08:35:54 -0800 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2017-02-16 04:02:44 -0800 |
| commit | f3213d9321735aa8e252d87796d5db43d4b830ec (patch) | |
| tree | c62feaa7d3d3e61aa5d1db29add1893eb175f687 /drivers/net/ethernet/intel/ixgbe/ixgbe.h | |
| parent | f215af8cae4c283d8a522ea166d94f763dc4aebf (diff) | |
| download | op-kernel-dev-f3213d9321735aa8e252d87796d5db43d4b830ec.zip op-kernel-dev-f3213d9321735aa8e252d87796d5db43d4b830ec.tar.gz | |
ixgbe: Update driver to make use of DMA attributes in Rx path
This patch adds support for DMA_ATTR_SKIP_CPU_SYNC and
DMA_ATTR_WEAK_ORDERING. By enabling both of these for the Rx path we are
able to see performance improvements on architectures that implement either
one due to the fact that page mapping and unmapping only has to sync what
is actually being used instead of the entire buffer. In addition by
enabling the weak ordering attribute enables a performance improvement for
architectures that can associate a memory ordering with a DMA buffer such
as Sparc.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ixgbe/ixgbe.h')
| -rw-r--r-- | drivers/net/ethernet/intel/ixgbe/ixgbe.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h b/drivers/net/ethernet/intel/ixgbe/ixgbe.h index 6530eff..8167e77 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h @@ -104,6 +104,9 @@ /* How many Rx Buffers do we bundle into one write to the hardware ? */ #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ +#define IXGBE_RX_DMA_ATTR \ + (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) + enum ixgbe_tx_flags { /* cmd_type flags */ IXGBE_TX_FLAGS_HW_VLAN = 0x01, |
