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author | Takashi Iwai <tiwai@suse.de> | 2017-09-04 14:50:49 +0200 |
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committer | Takashi Iwai <tiwai@suse.de> | 2017-09-04 14:50:49 +0200 |
commit | b06898d119f6b8dba7b318ad73558ce2d39161e8 (patch) | |
tree | df85bc0cd9047202faa6b02ee8ce706f155ba896 /drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c | |
parent | b24a5f293058b512f1685930f2983a20ee3e15ab (diff) | |
parent | f5fd4a67bef5f2c5c2c9eb0cb2900e12d192ae23 (diff) | |
download | op-kernel-dev-b06898d119f6b8dba7b318ad73558ce2d39161e8.zip op-kernel-dev-b06898d119f6b8dba7b318ad73558ce2d39161e8.tar.gz |
Merge tag 'asoc-v4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
ASoC: Updates for v4.14
This is quite a large release by volume of patches and diff, a lot of
that is mechanical cleanup patches but it's great to also see a range of
vendors actively working on adding new features and fixing issues in
their drivers. Intel and Realtek have been especially active here.
- Continued work towards moving everything to the component model from
Morimoto-san.
- Use of devres for jack detection GPIOs, eliminating some potential
resource leaks.
- Jack detection support for Qualcomm MSM8916.
- Support for Allwinner H3, Cirrus Logic CS43130, Intel Kabylake
systems with RT5663, Realtek RT274, TI TLV320AIC32x6 and Wolfson
WM8523.
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c')
-rw-r--r-- | drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c b/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c index ac7a150..2b85b87 100644 --- a/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c +++ b/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c @@ -2888,6 +2888,24 @@ static int cxgb4vf_pci_probe(struct pci_dev *pdev, */ adapter->name = pci_name(pdev); adapter->msg_enable = DFLT_MSG_ENABLE; + + /* If possible, we use PCIe Relaxed Ordering Attribute to deliver + * Ingress Packet Data to Free List Buffers in order to allow for + * chipset performance optimizations between the Root Complex and + * Memory Controllers. (Messages to the associated Ingress Queue + * notifying new Packet Placement in the Free Lists Buffers will be + * send without the Relaxed Ordering Attribute thus guaranteeing that + * all preceding PCIe Transaction Layer Packets will be processed + * first.) But some Root Complexes have various issues with Upstream + * Transaction Layer Packets with the Relaxed Ordering Attribute set. + * The PCIe devices which under the Root Complexes will be cleared the + * Relaxed Ordering bit in the configuration space, So we check our + * PCIe configuration space to see if it's flagged with advice against + * using Relaxed Ordering. + */ + if (!pcie_relaxed_ordering_enabled(pdev)) + adapter->flags |= ROOT_NO_RELAXED_ORDERING; + err = adap_init0(adapter); if (err) goto err_unmap_bar; |