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authorAl Viro <viro@ftp.linux.org.uk>2008-01-13 14:18:15 +0000
committerJeff Garzik <jeff@garzik.org>2008-01-18 14:44:33 -0500
commit5b5119167b724f4c4d54e69f91f22a83b01207af (patch)
tree60b6b72064cac9a278b67428d4f22d28851766e3 /drivers/net/dl2k.h
parent96d768517eef3c10d4a82bd121caa42f584082cb (diff)
downloadop-kernel-dev-5b5119167b724f4c4d54e69f91f22a83b01207af.zip
op-kernel-dev-5b5119167b724f4c4d54e69f91f22a83b01207af.tar.gz
dl2k: MSCR, MSSR, ESR, PHY_SCR fixes
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/dl2k.h')
-rw-r--r--drivers/net/dl2k.h40
1 files changed, 2 insertions, 38 deletions
diff --git a/drivers/net/dl2k.h b/drivers/net/dl2k.h
index c8aacf2..5f00ecb 100644
--- a/drivers/net/dl2k.h
+++ b/drivers/net/dl2k.h
@@ -385,19 +385,6 @@ enum _mii_aner {
};
/* MASTER-SLAVE Control Register */
-typedef union t_MII_MSCR {
- u16 image;
- struct {
- u16 _bit_7_0:8; // bit 7:0
- u16 media_1000BT_HD:1; // bit 8
- u16 media_1000BT_FD:1; // bit 9
- u16 port_type:1; // bit 10
- u16 cfg_value:1; // bit 11
- u16 cfg_enable:1; // bit 12
- u16 test_mode:3; // bit 15:13
- } bits;
-} MSCR_t, *PMSCR_t;
-
enum _mii_mscr {
MII_MSCR_TEST_MODE = 0xe000,
MII_MSCR_CFG_ENABLE = 0x1000,
@@ -408,20 +395,6 @@ enum _mii_mscr {
};
/* MASTER-SLAVE Status Register */
-typedef union t_MII_MSSR {
- u16 image;
- struct {
- u16 idle_err_count:8; // bit 7:0
- u16 _bit_9_8:2; // bit 9:8
- u16 lp_1000BT_HD:1; // bit 10
- u16 lp_1000BT_FD:1; // bit 11
- u16 remote_rcv_status:1; // bit 12
- u16 local_rcv_status:1; // bit 13
- u16 cfg_resolution:1; // bit 14
- u16 cfg_fault:1; // bit 15
- } bits;
-} MSSR_t, *PMSSR_t;
-
enum _mii_mssr {
MII_MSSR_CFG_FAULT = 0x8000,
MII_MSSR_CFG_RES = 0x4000,
@@ -433,17 +406,6 @@ enum _mii_mssr {
};
/* IEEE Extened Status Register */
-typedef union t_MII_ESR {
- u16 image;
- struct {
- u16 _bit_11_0:12; // bit 11:0
- u16 media_1000BT_HD:2; // bit 12
- u16 media_1000BT_FD:1; // bit 13
- u16 media_1000BX_HD:1; // bit 14
- u16 media_1000BX_FD:1; // bit 15
- } bits;
-} ESR_t, *PESR_t;
-
enum _mii_esr {
MII_ESR_1000BX_FD = 0x8000,
MII_ESR_1000BX_HD = 0x4000,
@@ -451,6 +413,7 @@ enum _mii_esr {
MII_ESR_1000BT_HD = 0x1000,
};
/* PHY Specific Control Register */
+#if 0
typedef union t_MII_PHY_SCR {
u16 image;
struct {
@@ -468,6 +431,7 @@ typedef union t_MII_PHY_SCR {
u16 xmit_fifo_depth:2; // bit 15:14
} bits;
} PHY_SCR_t, *PPHY_SCR_t;
+#endif
typedef enum t_MII_ADMIN_STATUS {
adm_reset,
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