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| author | Divy Le Ray <divy@chelsio.com> | 2007-11-16 11:22:16 -0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2008-01-28 15:04:11 -0800 |
| commit | a2604be5488095657aeb1a09c3f08d9f760132ec (patch) | |
| tree | eb90977bf4c9608b2e84658466170a8146ee5830 /drivers/net/cxgb3/regs.h | |
| parent | 3e5192eec8faf1df77514d2a593d14cc851a6b43 (diff) | |
| download | op-kernel-dev-a2604be5488095657aeb1a09c3f08d9f760132ec.zip op-kernel-dev-a2604be5488095657aeb1a09c3f08d9f760132ec.tar.gz | |
cxgb3 - HW set up updates
Disable PEX errors. The HW generates false positives.
Update RSS hash function to a symmetric algorithm.
Update T3C HW support
Signed-off-by: Divy Le Ray <divy@chelsio.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/cxgb3/regs.h')
| -rw-r--r-- | drivers/net/cxgb3/regs.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/cxgb3/regs.h b/drivers/net/cxgb3/regs.h index 6e12bf4..70e1961 100644 --- a/drivers/net/cxgb3/regs.h +++ b/drivers/net/cxgb3/regs.h @@ -965,6 +965,12 @@ #define V_LOCKTID(x) ((x) << S_LOCKTID) #define F_LOCKTID V_LOCKTID(1U) +#define S_TABLELATENCYDELTA 0 +#define M_TABLELATENCYDELTA 0xf +#define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA) +#define G_TABLELATENCYDELTA(x) \ + (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA) + #define A_TP_PC_CONFIG2 0x34c #define S_CHDRAFULL 4 @@ -1146,6 +1152,10 @@ #define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE) #define F_RQFEEDBACKENABLE V_RQFEEDBACKENABLE(1U) +#define S_HASHTOEPLITZ 2 +#define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ) +#define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U) + #define S_DISABLE 0 #define A_TP_TM_PIO_ADDR 0x418 @@ -1198,6 +1208,14 @@ #define A_TP_INT_ENABLE 0x470 +#define S_FLMTXFLSTEMPTY 30 +#define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY) +#define F_FLMTXFLSTEMPTY V_FLMTXFLSTEMPTY(1U) + +#define S_FLMRXFLSTEMPTY 29 +#define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY) +#define F_FLMRXFLSTEMPTY V_FLMRXFLSTEMPTY(1U) + #define A_TP_INT_CAUSE 0x474 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8 @@ -1291,6 +1309,10 @@ #define A_ULPTX_CONFIG 0x580 +#define S_CFG_CQE_SOP_MASK 1 +#define V_CFG_CQE_SOP_MASK(x) ((x) << S_CFG_CQE_SOP_MASK) +#define F_CFG_CQE_SOP_MASK V_CFG_CQE_SOP_MASK(1U) + #define S_CFG_RR_ARB 0 #define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB) #define F_CFG_RR_ARB V_CFG_RR_ARB(1U) |
