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authorMichael Chan <mchan@broadcom.com>2008-01-29 21:35:05 -0800
committerDavid S. Miller <davem@davemloft.net>2008-01-31 19:27:14 -0800
commit2726d6e126c0c16efeba30356d4ae105f1854d1e (patch)
treee952b9ab7aebe5822d1ec9379f247708422221bf /drivers/net/bnx2.h
parent6f743ca052575a26439d796249d9e7740b8192d7 (diff)
downloadop-kernel-dev-2726d6e126c0c16efeba30356d4ae105f1854d1e.zip
op-kernel-dev-2726d6e126c0c16efeba30356d4ae105f1854d1e.tar.gz
[BNX2]: Remove REG_WR_IND/REG_RD_IND macros.
The REG_WR_IND/REG_RD_IND macros are unnecessary and obfuscate the code. Many callers to these macros read and write shared memory from the bp->shmem_base, so we add 2 similar functions that automatically add the shared memory base. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.h')
-rw-r--r--drivers/net/bnx2.h9
1 files changed, 0 insertions, 9 deletions
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 7a1eff4..fb3c019 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -6805,9 +6805,6 @@ struct bnx2 {
int irq_nvecs;
};
-static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
-static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
-
#define REG_RD(bp, offset) \
readl(bp->regview + offset)
@@ -6817,12 +6814,6 @@ static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
#define REG_WR16(bp, offset, val) \
writew(val, bp->regview + offset)
-#define REG_RD_IND(bp, offset) \
- bnx2_reg_rd_ind(bp, offset)
-
-#define REG_WR_IND(bp, offset, val) \
- bnx2_reg_wr_ind(bp, offset, val)
-
/* Indirect context access. Unlike the MBQ_WR, these macros will not
* trigger a chip event. */
static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
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