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authorManuel Lauss <manuel.lauss@googlemail.com>2009-10-04 14:55:24 +0200
committerRalf Baechle <ralf@linux-mips.org>2010-02-27 12:52:50 +0100
commit9bdcf336d0c061e77f4c45c7b2bc32e3ed6b57e3 (patch)
tree9cce0d50bb1709654fae719e7175da25279402bc /drivers/mtd
parentebc89718a4b3fa0e440151fb4484541700828a5d (diff)
downloadop-kernel-dev-9bdcf336d0c061e77f4c45c7b2bc32e3ed6b57e3.zip
op-kernel-dev-9bdcf336d0c061e77f4c45c7b2bc32e3ed6b57e3.tar.gz
MIPS: Alchemy: devboard register abstraction
All Alchemy development boards have external CPLDs with a few registers in them. They all share an identical register layout with only a few minor differences (except the PB1000) in bit functions and base addresses. This patch - adds a primitive facility to initialize and use these external registers, - replaces all occurrences of bcsr->xxx accesses with calls to the new functions (the pb1200 cascade irq handling code is special). - collects BCSR register information scattered throughout the board headers in a central place. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/au1550nd.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index 92c334f..43d46e4 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -19,6 +19,7 @@
#include <asm/io.h>
#include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-db1x00/bcsr.h>
/*
* MTD structure for NAND controller
@@ -475,7 +476,8 @@ static int __init au1xxx_nand_init(void)
/* set gpio206 high */
au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
- boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1);
+ boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
+
switch (boot_swapboot) {
case 0:
case 2:
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