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authorScott Wood <scottwood@freescale.com>2013-04-10 17:34:37 -0500
committerDavid Woodhouse <David.Woodhouse@intel.com>2013-08-05 19:09:39 +0100
commit20cd0008bb01ea0f5dd5779896bf6f069aab9c8a (patch)
tree63b767ed9083bd2c251cab328a6cfceaacf3827d /drivers/mtd/nand/fsl_ifc_nand.c
parent435796889d714ffaf90923cfea868d8b5d28008c (diff)
downloadop-kernel-dev-20cd0008bb01ea0f5dd5779896bf6f069aab9c8a.zip
op-kernel-dev-20cd0008bb01ea0f5dd5779896bf6f069aab9c8a.tar.gz
mtd: fsl_ifc_nand: set NAND_NO_SUBPAGE_WRITE
This controller only does ECC on full-page accesses, even though the ECC consists of multiple steps. fsl_elbc_nand can get away with this because the ECC of an all-0xff region will be all-0xff, but this is not true with the ECC algorithms used by IFC. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/nand/fsl_ifc_nand.c')
-rw-r--r--drivers/mtd/nand/fsl_ifc_nand.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 180bfa7..317a771 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -823,7 +823,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
/* set up nand options */
chip->bbt_options = NAND_BBT_USE_FLASH;
-
+ chip->options = NAND_NO_SUBPAGE_WRITE;
if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
chip->read_byte = fsl_ifc_read_byte16;
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